ncp5423dr2g ON Semiconductor, ncp5423dr2g Datasheet - Page 14

• Manufacturer Part Number: ncp5423dr2g
• Description: Dual Outofphase Synchronous Buck Controller With Current Limit
• Manufacturer: ON Semiconductor

the intrinsic resistance of the inductor. A model of an
inductor (Figure 9) reveals that the windings of an inductor
have an effective series resistance (ESR).
measured with a simple parallel circuit: an RC integrator. If
the value of R
then the voltage measured across the capacitor C will be:
value of 0.1 mF is recommended. The value of R
selected according to:
Consult manufacturer’s datasheet for specific details.
current limit of:
20 A. If an increased current limit is required, a resistor
divider can be added.
winding resistance of the inductor are that efficiency is
maximized and heat generation is minimized. The tolerance
of the inductor ESR must be factored into the design of the
current limit. Finally, one or two more components are
required for this approach than with resistor sensing. Note
that, in the example of Figure 9, the IS+ input bias current
flowing through RS1 will introduce a small offset error. If
RS1 = 4 kW, at the maximum bias current limit of 1 mA, the
error will be 4 mV. This error can be avoided by using two
separate resistors, each half the calculated value, as shown
(R1 through R4) in the typical application circuit of
Figure 1.
Adding External Slope Compensation
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
Inductor ESR.
The voltage drop across the inductor ESR can be
Selecting Components.
Typical values for inductor ESR range in the low mW.
Selection of components at these values will result in a
Given an ESR value of 3.5 mW, the current limit becomes
The advantages of setting the current limit by using the
Today’s voltage regulators are expected to meet very
V
GATE(H)
IS+
IS−
GATE(L)
CC
Figure 9. Inductor ESR Current Sensing
S1
and C are chosen such that:
Another means of sensing current is to use
V C + ESR
R S1 +
I LIM + 0.070 V
ESR
L
RS1
L
+ R S1 C
Select the capacitor C first. A
ESR
ESR
1
ESR
I LIM
C
C
NCP5422A, NCP5423
S1
http://onsemi.com
can be
Co
14
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (V
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
internal slope compensation is insufficient, the performance
of the NCP5422A−based regulator can be improved through
the addition of a fixed amount of external slope
compensation at the output of the PWM Error Amplifier (the
COMP pin) during the regulator off−time. Referring to
Figure 10, the amount of voltage ramp at the COMP pin is
dependent on the gate voltage of the lower (synchronous)
FET and the value of resistor divider formed by R1and R2.
where:
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
V SLOPECOMP + V GATE(L)
V
V
R1, R2 = voltage divider resistors;
t = t
t = RC constant determined by C1 and the parallel
The artificial voltage ramp created by the slope
As a consequence of large currents being turned on and off
NCP5422A
SLOPECOMP
GATE(L)
combination of R1, R2 neglecting the low driver
output impedance.
ON
Proper Voltage Ramp at the Beginning of
GATE(L)
Figure 10. Small RC Filter Provides the
COMP
or t
= lower MOSFET gate voltage;
OFF
= amount of slope added;
(switch off−time);
EMI MANAGEMENT
Each On−Time Cycle
R2
C
COMP
R1 ) R2
R2
To Synchronous
C1
FET
(1 * e
R1
−t
FB
t )
),