dm9301 ETC-unknow, dm9301 Datasheet - Page 7

• Manufacturer Part Number: dm9301
• Description: 100mbps Ethernet Fiber/twisted Pair Single Chip Media Converter
• Manufacturer: ETC-unknow

Final
Version: DM9301-DS-F02
May 8, 2000
LED Interface(Continued)
Diagnostic Port Interface
79, 77,
76, 74,
48, 47,
45, 44,
52
36
35
96
97
73
70
43
71
RXD0, RXD1,
RXD2, RXD3,
TXERRLED#
TXD0, TXD1,
TXD2, TXD3,
FXALPBK
TXALPBK
FXDLPBK
TXDLPBK
RXCLK
TXCLK
RXD4
TXD4
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
OD
O
O
0
I
I
I
I
I
TX Error LED:
Indicates an error was detected by the TX Code Group
Alignment Monitor function on the TX receiver. Active
low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the TXERRLED output. This ensures that even
minimum size errors generate adequate LED ON to
insure visibility.
FX Interface Analog Loop Back:
Loops the FX NRZI analog transmit data path to the FX
NRZI analog receive path.
Initiated at a H/W reset. Active high.
TX Interface Analog Loop Back:
Loops the TX NRZI analog transmit data path to the TX
NRZI analog receive path.
Initiated at a H/W reset. Active high.
FX Interface Digital Loop Back:
Loops the FX 5-bit symbol digital transmit data path to
the FX 5-bit symbol digital receive path.
Initiated at a H/W reset. Active high.
TX Interface Digital Loop Back:
Loops the TX 5-bit symbol digital transmit data path to
the TX 5-bit symbol digital receive path.
Initiated at a H/W reset. Active high.
Receive Data 4 through 0:
The receive data 5-bit symbol interface. Data is clocked
out on the falling edge of RXCLK.
Receive Clock:
25 Mhz recovered clock, clock source is selected by the
MUXCTL1 and MUXCTL0.
Transmit Data 4 through 0:
The transmit data 5-bit symbol interface. Data is clocked
in on the rising edge of TXCLK.
Transmit Clock:
25 Mhz recovered clock, clock source is selected by the
MUXCTL1 and MUXCTL0.
DM9301
7