lt3579iufd-trpbf Linear Technology Corporation, lt3579iufd-trpbf Datasheet - Page 16

• Manufacturer Part Number: lt3579iufd-trpbf
• Description: Lt3579/lt3579-1 6a Boost/inverting Dc/dc Converter With Fault Protection Features
• Manufacturer: Linear Technology Corporation

LT3579/LT3579-1
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
• To optimize thermal performance, solder the exposed
• A ground plane should be used under the switcher circuitry
• High speed switching path (see specifi c topology below for
• The V
• Place the bypass capacitor for the V
16
ground pad of the LT3579 to the ground plane with
multiple vias around the pad connecting to additional
ground planes.
to prevent interplane coupling and overall noise.
more information) must be kept as short as possible.
close to the LT3579 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
close as possible to the LT3579.
C
, FB, and RT components should be placed as
V
–
+
IN
A– RETURN C
WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN C
C
OUT
Figure 9. Suggested Component Placement for Boost Topology in FE20 Package
AND C
OUT1
C
IN
OUT
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
IN
GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C
AND C
GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
OUT1
L1
GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE
A
IN
pin (C
10
1
2
3
4
5
6
7
8
9
VIN
) as
21
• Place the bypass capacitor for the inductor (C
• Bypass capacitors, C
• The load should connect directly to the positive and
Boost Topology Specifi c Layout Guidelines
• Keep length of loop (high speed switching path)
SEPIC Topology Specifi c Layout Guidelines
• Keep length of loop (high speed switching path) governing
20
19
18
17
16
15
14
13
12
11
close as possible to the inductor.
into a single bypass capacitor, C
inductor can be close to the V
negative terminals of the output capacitor for best load
regulation.
governing switch, diode D1, output capacitor C
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
switch, fl ying capacitor C1, diode D1, output capacitor C
and ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
D2
GND
B
C
OUT1
D1
M1
C
OUT
PWR
3579 F08
IN
and C
GROUND
SYNC
SHDN
CLKOUT
V
–
+
OUT
IN
IN
VIN
, if the input side of the
pin of the LT3579.
, may be combined
OUT
PWR
, and
35791f
OUT
) as
,