ncp3418 ON Semiconductor, ncp3418 Datasheet

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ncp3418

Manufacturer Part Number
ncp3418
Description
Dual Bootstrapped 12 V Mosfet Driver
Manufacturer
ON Semiconductor
Datasheet

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NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
optimized to drive the gates of both high- -side and low- -side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
ADP3418 with the following advantages:
Features
© Semiconductor Components Industries, LLC, 2007
April, 2007 - - Rev. 13
The NCP3418 and NCP3418A are dual MOSFET gate drivers
With a wide operating voltage range, high or low side MOSFET
The floating top driver design can accommodate VBST voltages as
The NCP3418 is pin- -to- -pin compatible with Analog Devices
MOSFET
Faster Rise and Fall Times
Internal Charge Pump Diode Reduces Cost and Parts Count
Thermal Shutdown for System Protection
Integrated OVP
Internal Pulldown Resistor Suppresses Transient Turn On of Either
Anti Cross- -Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 10.x Specifications
Undervoltage Lockout
Thermally Enhanced Package Available
Pb- -Free Packages are Available
1
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
8
8
1
1
ORDERING INFORMATION
341x
A
L
Y
WW, W = Work Week
G
BST
V
OD
CC
PIN CONNECTIONS
IN
http://onsemi.com
CASE 751AC
PD SUFFIX
CASE 751
D SUFFIX
1
SO- -8 EP
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Pb--Free Package
SO- -8
x = 8 or 8A
Publication Order Number:
8
8
1
8
1
DRVH
SW
PGND
DRVL
DIAGRAMS
MARKING
AYWW
ALYW
341x
341x
NCP3418/D
G

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ncp3418 Summary of contents

Page 1

... An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP3418A is identical to the NCP3418 except that there is no internal charge pump diode. The NCP3418 is pin- -to- -pin compatible with Analog Devices ...

Page 2

... BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this boot- strap voltage for the high--side MOSFET switched. The recommended capacitor value is between 100 nF and 1.0 mF. An external diode will be needed with the NCP3418A Logic--Level Input. This pin has primary control of the drive outputs. ...

Page 3

MAXIMUM RATINGS Operating Ambient Temperature Operating Junction Temperature, T (Note 1) J Package Thermal Resistance: SO--8 Junction--to--Case, R θJC Junction--to--Ambient, R (2--Layer Board) θJA Package Thermal Resistance: SO--8 EP Junction--to--Ambient, R (Note 2) θJA Storage Temperature Range, T ...

Page 4

... NCP3418- -SPECIFICATIONS (Note 5) (V Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time (Note 6) PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH- -SIDE DRIVER Output Resistance, Sourcing Current ...

Page 5

OD t pdlOD DRVH or DRVL IN t pdlDRVL DRVL 90% 1.5 V DRVH--SW SW Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted) 90% Figure 2. Output Disable Timing Diagram t ...

Page 6

IN DRVH DRVL Figure 4. DRVH Rise and DRVL Fall Times 40 30 trTG 20 trBG LOAD CAPACITANCE (nF) Figure 6. Rise Time vs. Load Capacitance Figure ...

Page 7

... V supply and PGND. CC When the NCP3418 is enabled, the low- -side driver’s output is 180_ out of phase with the PWM input. When the device is disabled, the low- -side gate is held low. High- -Side Driver ...

Page 8

... G C SEATING PLANE - - 0.25 (0.010 *For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC CASE 751--07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 9

... MAX A 1.35 1. 0.00 0.10 A2 1.35 1.65 b 0.31 0.51 b1 0.28 0. 0.17 0.25 c1 0.17 0.23 D 4.90 BSC E 6.00 BSC c E1 3.90 BSC e 1.27 BSC L 0.40 1.27 L1 1.04 REF ( 2.24 3.20 G 1.55 2.51 h 0.25 0. θ Exposed Pad   mm SCALE 6:1 inches ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP3418/D ...

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