lx1688 Microsemi Corporation, lx1688 Datasheet - Page 8

• Manufacturer Part Number: lx1688
• Description: Multiple Lamp Ccfl Controller
• Manufacturer: Microsemi Corporation

Copyright © 2001
Rev. 1.2, 2006-03-09
and may or may not be externally synchronized to the LCD
video frame rate. It will directly gate the signal BRT.
CPWM should not be used in this case.
F
maximum numbers of strike attempts has occurred without
lamp ignition. In this condition the FAULT pin will go
active high with typically 20mA drive capability. Holding
the OLSNS pin low (<200mV) will also force timeout and
activate the FAULT pin. When used as a master, fault
condition true does not inhibit master clock outputs
PHA_SYNC and RMP_RST.
I_R P
internal ramp frequency, which is proportional to a bias
current set by resistor RI of 80.6K. The output frequency
can thus be adjusted by varying the value of RI-R, the
typical range from about 50K to 100K. Since there is some
variation in the frequency due to change in the input supply
(VDD) it is recommended that the value of RI-R be selected
at the nominal input voltage.
S
(VDDSW)
operated systems, a very low power sleep mode is included.
The IC will consume less than 10µA quiescent current from
both the VDD and VDD_P pins combined, when the
ENABLE pin is deactivated. The polarity of the ENABLE
pin is programmable by the BEPOL input (see table 1). In
addition the controller provides a switched supply pin
VDDSW this output supplies at least 10mA at VDD ─ .2V
for external circuitry. This output can be used to power
additional circuitry that can be enabled with the controller.
LEEP
AULT
Formula 1:
Triangular Wave Generator Frequency, F
Formula 3:
Minimum Current Error Amp Bandwidth, BW
Formula 5:
Softstart time, T
The fault pin is a digital output that indicates that the
The run mode frequency of the output is one half the
Since the LX1688 can be used in portable battery
IN
TM
P
M
IN
ODE
T
SS
F
B
TRI
(ENABLE S
WIEA_MIN
=
SS
4
=
,
500
(
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: [phone]
25
,
=
×
000
R ×
. 0
IGNAL
1
C
I
000048
×
ICOMP
C
C
TRI
VCOMP
)
AND
)
TRI
B I A S & T I M I N G E Q U A T I O N S
[Hz]
[Hz]
[sec]
D E T A I L E D D E S C R I P T I O N
S
IEA_MIN
WITCHED
Integrated Products Division
®
Microsemi
VDD
RangeMAX™
RMP_RST
WITH
operation, and RMP_RST and PHA_SYNC is supplied
from an external source, the signal timing should be met as
outlined below.
frequency and duty should be 10 to 13%, and PHA_SYNC
should be generated by divide by 2 of RMP_RST signal.
Phase of these signals should be met the as shown, note the
delay between the RMP_RST and PHA_SYNC signals:
T3 duty is 50% of operating frequency.
When the LX1688 is configured for slave mode
RMP_RST should be 2 times frequency of lamp
Formula 2:
Lamp Frequency (A
Formula 4:
Minimum Voltage Error Amp Bandwidth, B
Formula 6:
Minimum Power-on Reset Pulse Width, T
Multiple Lamp CCFL Controller
S
LAVE
Tr, Tf
T1
T1
T2
T3
T2
P
AND
T
F
B
M
RODUCTION
LAMP
MIN_POR
WVEA_MIN
ODE
PHA_SYNC
=
O
OUT
Min
150
10
49
PERATION
=
’s switching frequency), F
200
=
2
3 .
D
0
e- ×
C
e ×
.
ATA
000048
Typ
250
6
50
1
12
VCOMP
PIN TIMING REQUIREMENT
C
S
R
POR
HEET
I
Max
100
13
51
T3
[Hz]
[sec]
[Hz]
MIN_POR
WVEA_MIN
LAMP
nsec
nsec
Unit
%
%
LX1688
Page 8