bd6761fs ROHM Co. Ltd., bd6761fs Datasheet - Page 19

• Manufacturer Part Number: bd6761fs
• Description: Motor Driver Ic Series For Printers Three-phase Brushless Motor Pre-driver For Paper Feed Us
• Manufacturer: ROHM Co. Ltd.

13)
14)
15)
Servo circuit (BD6762FV)
Speed lock detection circuit (BD6762FV)
Motor locking protection (BD6762FV)
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An IC with a built-in the frequency multiplication circuit.
Servo circuit is composed of the feedback loop as shown in the diagram and flows in/out the current (22μA: Typ.) to the LPF pin (30
pin) by detecting the phase difference between the CLKIN pin (29 pin) and the frequency dividing unit output FCOMP. The phase
difference signal output to the LPF pin (30 pin) is smoothed by the filter which is connected at the IC external of the LPF pin (30 pin)
and this voltage is input to the VCO (Voltage control oscillation circuit) to determine the frequency for the internal signal FVCO. Since
the dividing ratio of this frequency dividing unit is set to 1024, the relation of:
can be obtained. The FCOMP and CLKIN have the same frequency according to the feedback loop as shown in the following
diagram. Therefore the multiplied frequency of 1024 times of FCOMP or CLKIN is acquired as the FVCO frequency.
The FGSOUT signal (28 pin), which detects the motor rotation speed and the reference clock in the IC, are compared and the
acceleration/deceleration signal is output to the DOUT pin (32 pin). Reference clock is the signal (FVCO) that the CLKIN signal (29
pin) is multiplied by 1024. When the FG period is short to the reference clock period, it is determined that the motor revolution speed
is too fast and the difference from the reference clock period is output to the DOUT pin as the deceleration command. When the FG
period is long, the difference is output as an accelerating command.
Phases of the FGSOUT (28 pin) signal, which detected the motor revolution speed and the CLKIN (29 pin) input from the external are
compared, and if the FG phase leads to CLKIN (28 pin), the difference is output as the deceleration command. If the FG phase lags,
the difference is output as the acceleration command.
Speed error of the reference clock, which is obtained in the speed discriminator block and the FG signal, and the phase difference
signal of the CLKIN acquired in PLL block and the FG are integrated together and smoothed to become the DC voltage. This
smoothed signal determines the PWM on-duty.
When the motor speed is within ±6.25% range to the CLKIN signal (29 pin), L is output to the LD pin (36 pin) output.
Since the LD pin (36 pin) has the open/drain output format, use as it is pulled up to the power supply with the resistor (100kΩ). At this
time, pay attention so that the voltage more than 36 V is not applied to the LD pin.
The motor locking protection circuit determines when the motor is in the locking condition. When the motor speed is not in the lock
range (preset value: ±6.25%) and the motor locking detection time T
turned off.
Motor locking protection can be cleared by making the condition Low, after setting the ST/SP pin or the SB pin to OPEN or making
high. Motor locking detection time T
(preset value: 96) of the internal counter.
Frequency multiplication circuit (Dividing period) (BD6762FV)
Speed discriminator (BD6762FV)
PLL (BD6762FV)
Integration amplifier (BD6762FV)
FVCO[Hz]=1024・FCOMP[Hz] ,
T
LP
CLKIN
FCOMP
=2×10
５
×C7×CLP [S]
Frequency dividing
unit (1024 dividing)
Phase comparator
LP
is determined by the capacitor C7 which is connected to the LP pin and the count number CLP
19/24
FVCO
VCO
oscillation circuit)
(Voltage
LP
elapsed, the high-side and low-side output gates are both
control
LPF