a6832eep Allegro MicroSystems, Inc., a6832eep Datasheet - Page 4

• Manufacturer Part Number: a6832eep
• Description: A6832 Dabic-5 32-bit Serial Input Latched Sink Drivers
• Manufacturer: Allegro MicroSystems, Inc.

NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specifi ed maximum clock frequency.
S
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
erial Data present at the input is transferred to the shift register on
OUT P UT E NAB LE
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
OUT P UT E NAB LE
Key
DAT A OUT
B
C
D
E
A
S T R OB E
DAT A IN
C LOC K
S E R IAL
S E R IAL
OUT
OUT
Data Active Time Before Clock Pulse (Data Set-Up Time)
Data Active Time After Clock Pulse (Data Hold Time)
Clock Pulse Width
Time Between Clock Activation and Strobe
Strobe Pulse Width
Timing Requirements and Specifi cations
N
N
A
DAT A
(Logic Levels are V
50%
B
C
Description
50%
HIG H = ALL OUT P UT S E NAB LE D
D
50%
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 [phone]
50%
t
p(C H-S QX)
t
dis (B Q)
50%
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
DD
E
t
and Ground)
p(S T H-QL)
t
10%
p(S TH-QH)
t
en(B Q)
DAT A
90%
t
DAT A
r
Symbol
t
t
w(STH)
t
t
w(CH)
t
su(D)
su(C)
h(D)
10%
90%
50%
Time (ns)
t
DAT A
f
100
25
25
50
50
A6832
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