r2j20652anp Renesas Electronics Corporation., r2j20652anp Datasheet
r2j20652anp
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r2j20652anp Summary of contents
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... Integrated Driver – MOS FET (DrMOS) Description The R2J20652ANP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose ...
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... R2J20652ANP Block Diagram DISBL# 2 μA CGND Reg5V 150 k LSDBL# Reg5V Input Logic PWM (TTL Level) (3 state in) CGND Notes: 1. Truth table for the DISBL# pin. DISBL# Input Driver Chip Status "L" Shutdown (GL "L") "Open" Shutdown (GL "L") "H" ...
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... R2J20652ANP Pin Arrangement VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name Pin No. LSDBL VCIN 3 BOOT 4 CGND 5, 37, Pad GH 6 VIN 8 to 14, Pad VSWH 7, 15 35, Pad ...
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... R2J20652ANP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Switch node voltage BOOT voltage Supply voltage PWM voltage Other I/O voltage Reg5V voltage Reg5V current DISBL# current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. ...
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... R2J20652ANP Recommended Operating Condition Item Symbol Input voltage VIN Supply voltage VCIN Electrical Characteristics Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM PWM rising threshold input PWM falling threshold PWM input resistance ...
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... VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL Preliminary +1.3 V Power GND Signal GND ...
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... VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL VCIN BOOT DISBL# VIN Reg5V VSWH R2J20652ANP PWM PGND CGND LSDBL Preliminary +1.1 V Power GND Signal GND ...
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... PWM VIN CGND DSBL# PAD PAD Reg5V CGND GL R2J20652ANP VSWH VSWH PAD Preliminary Low Side Disable Signal INPUT CGND PWM INPUT DSBL# INPUT 1.0 μ ...
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... OUT O O Efficiency = OUT IN P (DrMOS – P LOSS 27°C REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page VCIN BOOT DISBL# VIN R2J20652ANP Reg5V VSWH LSDBL# PWM PGND CGND GH GL CIN OUT Preliminary Electric I O load Average Output Voltage Averaging ...
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... R2J20652ANP Typical Data Power Loss vs. Output Current 9 VIN = VCIN = Reg5V = 5 V VOUT = 1 600 kHz 7 PWM L = 0.45 μ Output Current (A) Power Loss vs. Output Voltage 1.5 VIN = 12 V VCIN = Reg5V = 600 kHz PWM L = 0.45 μH IOUT = 25 A 1.3 1.2 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) REJ03G1867-0300 Rev ...
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... R2J20652ANP Power Loss vs. Output Inductance 1.5 VIN = 12 V VCIN = Reg5V = 5 V 1.4 VOUT = 1 600 kHz PWM IOUT = 25 A 1.3 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (μH) Average ICIN vs. Switching Frequency 50 VIN = 12 V VCIN = Reg5V = 5 V VOUT = 1 0.45 μH IOUT = 250 500 750 Switching Frequency (kHz) REJ03G1867-0300 Rev ...
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... R2J20652ANP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low- side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & ...
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... R2J20652ANP PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. PWM The LSDBL# pin is the Low Side Gate Disable pin for " ...
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... R2J20652ANP The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri- state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 100 ns (typ.). After the tri-state mode has been entered and GH and GL have become low, a PWM input voltage of 3 ...
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... Figure 4 Equivalent Circuit for the PWM-pin Input MOS FETs The MOS FETs incorporated in R2J20652ANP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin ...
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... RENESAS Code P-HVQFN40-p-0606-0.50 PVQN0040KC HD INDEX 1.95 2-A section CAV No. Die No. 1. Ordering Information Part Name R2J20652ANP#G3 REJ03G1867-0300 Rev.3.00 Feb 26, 2010 Page Previous Code MASS[Typ.] — — 4-C0.50 1pin Quantity 2500 pcs ...
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... Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 Notice © 2010 Renesas Electronics Corporation. All rights reserved. http://www.renesas.com Colophon 1.0 ...