r2j20651np Renesas Electronics Corporation., r2j20651np Datasheet
r2j20651np
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r2j20651np Summary of contents
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... Integrated Driver – MOS FET (DrMOS) Description The R2J20651NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap Schottky barrier diode (SBD), eliminating the need for an external SBD for this purpose ...
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... R2J20651NP Block Diagram VCIN THWN THWN CGND DISBL# 0.5 µA VCIN CGND 150 k LSDBL# VCIN PWM Input logic (TTL level) (3 state in) CGND Notes: 1. Truth table for the DISBL# pin. DISBL# Input Driver Chip Status "L" Shutdown (GL "L") "Open" Shutdown (GL "L") " ...
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... R2J20651NP Pin Arrangement VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name Pin No. LSDBL# 1 VCIN 2 VDRV 3 BOOT 4 CGND 5, 37, Pad GH 6 VIN 8 to 14, Pad VSWH 7, 15 35, Pad ...
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... R2J20651NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Supply voltage & Drive voltage Switch node voltage BOOT voltage I/O voltage Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110°C. 2. Rated voltages are relative to voltages on the CGND and PGND pins. ...
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... R2J20651NP Electrical Characteristics Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM PWM rising threshold input PWM falling threshold PWM input resistance Tri-state shutdown window Shutdown hold-off time DISBL# Disable threshold input Enable threshold ...
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... Page 0.1 µF 0~10 Ω VIN CGND PAD PAD 13 VIN 14 15 VSWH R2J20651NP 16 PGND 17 VSWH PAD Preliminary 1.0 µF CGND Low Side Disable Signal INPUT CGND 2 1 PWM 40 PWM INPUT DISBL# 39 THWN ...
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... R2J20651NP Typical Application ( Input Power + PWM1 PWM PWM2 Control PWM3 Circuit PWM4 REJ03G1743-0100 Rev.1.00 Dec 01, 2008 Page VCIN VDRV BOOT GH THWN VIN R2J20651 DISBL# VSWH NP LSDBL# PGND PWM CGND GL VCIN VDRV BOOT GH THWN VIN R2J20651 DISBL# VSWH ...
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... R2J20651NP ( Input Power +5 V PWM1 PWM PWM2 Control PWM3 Circuit PWM4 REJ03G1743-0100 Rev.1.00 Dec 01, 2008 Page VCIN VDRV BOOT GH THWN VIN R2J20651 DISBL# VSWH NP LSDBL# PGND PWM CGND GL VCIN VDRV BOOT GH THWN VIN R2J20651 DISBL# VSWH NP LSDBL# PGND PWM ...
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... R2J20651NP Test Circuit I IN Vinput A I CIN Vcont A V CIN 5V pulse f PWM × V × V Note CIN × OUT O O Efficiency = OUT IN P (DrMOS LOSS 27°C REJ03G1743-0100 Rev.1.00 Dec 01, 2008 Page 6.2 Ω V 0.1 µF VCIN VDRV ...
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... R2J20651NP Typical Data Power Loss vs. Output Current 10 VIN = VCIN = 5 V VOUT = 1 600 kHz PWM L = 0.45 µ Output Current (A) Power Loss vs. Output Voltage 1.5 VIN = 12 V VCIN = 600 kHz PWM L = 0.45 µH 1.3 IOUT = 25 A 1.2 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) REJ03G1743-0100 Rev ...
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... R2J20651NP Typical Data (cont.) Power Loss vs. Output Inductance 1.5 VIN = 12 V VCIN = 5 V 1.4 VOUT = 1 600 kHz PWM 1.3 IOUT = 25 A 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (µH) Average ICIN vs. Switching Frequency 50 VIN = 12 V VCIN = 5 V VOUT = 1 0.45 µH IOUT = 250 500 750 Switching Frequency (kHz) REJ03G1743-0100 Rev ...
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... R2J20651NP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low- side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & ...
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... R2J20651NP DCM Operation (LSDBL# = "L" Figure 1.2 Typical Signals During Low-Side Disable Operation The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri- state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in the input hysteresis window for 240 ns (typ ...
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... Logic Level MOS FETs The MOS FETs incorporated in R2J20651NP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low- side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. ...
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... Moreover, by taking the wide VSWH pattern, the effect of letting the heat from the low side MOS FET can be expected. When R2J20651NP is mounted on a small substrate like POL module, the temperature rising of the device could be eased if the thermal via-hole is added under the pad of VIN and VSWH. ...
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... R2J20651NP Footprint Example 0.20 0.6 REJ03G1743-0100 Rev.1.00 Dec 01, 2008 Page 6.20 C0.4 13–R0.2 0.50 40–0.30 Figure 5 Footprint Example Preliminary (Unit: mm) 0.20 2.3 0.6 0.3 C0.1 2.15 ...
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... P-HVQFN40-p-0606-0.50 PVQN0040KC HD INDEX 1.95 2-A section CAV No. Die No. 1. Ordering Information Part Name R2J20651NP-G3 R2J20651NP-13 REJ03G1743-0100 Rev.1.00 Dec 01, 2008 Page Previous Code MASS[Typ.] — — 4-C0.50 1pin Quantity 2500 pcs 250 pcs ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...