r2j20651anp Renesas Electronics Corporation., r2j20651anp Datasheet - Page 15

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r2j20651anp

Manufacturer Part Number
r2j20651anp
Description
Integrated Driver ? Mos Fet Drmos
Manufacturer
Renesas Electronics Corporation.
Datasheet
R2J20651ANP
PCB Layout Example
Figure 5 shows an example of the PCB layout for the R2J20651ANP. Placing several ceramic capacitors (e.g. 10 μF)
between VIN and PGND can be expected to the decreasing switching noise and improvement of efficiency.
In that case, it is necessary to connect each GND pattern with low impedance by using other PCB layers.
Moreover, by taking the wide VSWH pattern, the effect of letting the heat from the low side MOS FET can be expected.
When R2J20651ANP is mounted on a small substrate like POL module, the temperature rising of the device could be
eased if the thermal via-hole is added under the pad of VIN and VSWH.
REJ03G1792-0100 Rev.1.00 Jun 03, 2009
Page 15 of 17
Figure 5 R2J20651ANP PCB Layout Example (Top View)
GND
VSWH
To Inductor
10 μF
10 μF
GND
DISBL#
PWM
Vin
GND
VCIN
1 μF
0.1 μF
Rboot
Via Hole
10 μF
10 μF
GND
Preliminary

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