r2j20658bnp Renesas Electronics Corporation., r2j20658bnp Datasheet
r2j20658bnp
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r2j20658bnp Summary of contents
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... Integrated Driver - MOS FET (DrMOS) Description The R2J20658BNP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating the need for an external SBD for this purpose ...
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... R2J20658BNP Block Diagram THWN THWN THDN DISBL# 2 μA CGND Reg5V CGND 160 k LSDBL# Reg5V Input Logic PWM (TTL Level) (3 state in) 3 state signal CGND Notes: 1. Truth table for the DISBL# pin DISBL# Input Driver Chip Status "L" Shutdown (GL "L") " ...
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... R2J20658BNP Pin Arrangement VIN VIN VIN VIN VSWH PGND PGND PGND PGND PGND Note: All die-pads (three pads in total) should be soldered to PCB. Pin Description Pin Name Pin No. LSDBL# 1 Reg5V 2 VCIN 3 BOOT 4 CGND 5, 37, Pad GH 6 VIN 8 to 14, Pad VSWH 7, 15 35, Pad ...
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... R2J20658BNP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Switch node voltage BOOT voltage Supply voltage PWM voltage Other I/O voltage Reg5V voltage Reg5V current THWN/THDN current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C. ...
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... R2J20658BNP Recommended Operating Condition Item Symbol Input voltage VIN Supply voltage & VCIN Drive voltage Electrical Characteristics Item Supply VCIN start threshold VCIN shutdown threshold UVLO hysteresis VCIN operating current VCIN disable current PWM PWM input high level input PWM input low level ...
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... Reg5V VSWH R2J20658BNP PWM PGND CGND LSDBL VCIN BOOT THWN VIN DISBL# Reg5V VSWH R2J20658BNP PWM PGND CGND LSDBL VCIN BOOT THWN VIN DISBL# Reg5V VSWH R2J20658BNP PWM PGND CGND LSDBL Preliminary +1.3 V Power GND Signal GND Page ...
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... PWM VIN CGND DISBL# PAD PAD THWN CGND R2J20658BNP GL VSWH VSWH PAD Preliminary Low-side Disable Signal INPUT CGND 40 PWM INPUT 39 Thermal Shutdown kΩ 36 VCIN 35 10 kΩ ...
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... OUT O O Efficiency = OUT IN P (DrMOS – P LOSS 27°C R07DS0550EJ0101 Rev.1.01 Sep 30, 2011 V VCIN BOOT DISBL# VIN R2J20658BNP Reg5V VSWH LSDBL# PWM PGND CGND GH GL CIN OUT Preliminary Electric I O load Averaging Output Voltage Averaging V V circuit ...
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... R2J20658BNP Typical Data Power Loss vs. Output Current 10 VIN = VCIN = Reg5V = 5 V VOUT = 1 600 kHz PWM L = 0.45 μ Output Current (A) Power Loss vs. Output Voltage 1.8 VIN = 12 V 1.7 VCIN = Reg5V = 600 kHz PWM 1 0.45 μH IOUT = 25 A 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 Output Voltage (V) R07DS0550EJ0101 Rev ...
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... R2J20658BNP Typical Data (cont.) Power Loss vs. Output Inductance 1.8 VIN = 12 V 1.7 VCIN = Reg5V = 5 V VOUT = 1 600 kHz PWM IOUT = 25 A 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Output Inductance (μH) Average ICIN vs. Switching Frequency 60 VIN = 12 V VCIN = Reg5V = 5 V VOUT = 1 0.45 μH IOUT = 250 500 ...
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... R2J20658BNP Description of Operation The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low- side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage. VCIN & ...
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... R2J20658BNP PWM & LSDBL# The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS FET (GH) is high and the gate of the low-side MOS FET (GL) is low. When the PWM input becomes middle voltage or high impedance, Zero Current Detection (ZCD) function works. ...
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... R2J20658BNP The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is low. This pin is internally pulled up to Reg5V with 160 k resistor. When low side disable function is not used, keep this pin open or pulled up to VCIN. ...
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... Figure 5.1 THDN Signal to the System Controller MOS FET The MOS FETs incorporated in R2J20658BNP are highly suitable for synchronous-rectification buck conversion. For the high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin. ...
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... JEITA Package Code RENESAS Code P-HVQFN40-p-0606-0.50 PVQN0040KE HD INDEX 1.95 2-A section CAV No. Die No. 1. Ordering Information Part Name R2J20658BNP#G0 R07DS0550EJ0101 Rev.1.01 Sep 30, 2011 Previous Code MASS[Typ.] — — 4-C0.50 1pin Quantity 2500 pcs Preliminary ...
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... Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 Notice © 2011 Renesas Electronics Corporation. All rights reserved. http://www.renesas.com Colophon 1.1 ...