r2j20701np Renesas Electronics Corporation., r2j20701np Datasheet
r2j20701np
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r2j20701np Summary of contents
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... R2J20701NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters ...
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... R2J20701NP Application Circuit Example SYNC REG5 TRK-SS Controller Chip FB EO SGND REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page VIN ( VOUT (1 ...
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... R2J20701NP Block Diagram REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page ...
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... R2J20701NP Pin Arrangement VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND Package: 56-pin QFN (8 mm Note: All die-pads (three pads in total) should be soldered to PCB. REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page ...
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... R2J20701NP Pin Description Pin Name Pin No. VIN Input voltage for the buck converter 21 Switching node. Connect a choke coil between the SW pin and dc output node of the converter. PGND Ground of the power stage. SGND 6, 52 Ground of the IC chip. ...
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... R2J20701NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage SYNC pin voltage Voltage on other pins REG5 current Ishare current TRK-SS dc current IREF current EO sink current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25° ...
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... R2J20701NP Electrical Characteristics Item Supply VIN start threshold VIN shutdown threshold UVLO hysteresis Input bias current Input shutdown current 5-V Output voltage regulator Line regulation Load regulation 5.25-V Output voltage regulator Remote Disable threshold On/off Enable threshold Input current Reference IREF pin voltage ...
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... R2J20701NP Item Current CS current ratio sense Leading edge blanking time CS comparator delay to output OCP comparator threshold on CS pin Hiccup interval RAMP offset voltage CS offset current Note: 1. These are reference values for design and have not been 100% tested in production. REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page (Ta = 25° ...
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... R2J20701NP Description of Operation Peak Current Control The control IC operates in a current-programmed control mode, in which the output of the converter is controlled by the choice of the peak current from the high-side MOS FET. The current from this MOS FET is sensed by an active current-sensing circuit (ACS), the output current of which is 1/18500 (54 ppm) of the MOS FET current. The ACS current is then converted to a certain voltage by the external resistor on the CS pin ...
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... R2J20701NP Oscillator and Pulse Generator The frequency of oscillation is set by the value of the external capacitor connected to the CT pin. This frequency is twice as high as the actual switching frequency. The frequencies are determined by the following equations: Oscillator frequency; Fct = 160 (CT( pF Switching frequency; Fsw = 0.5 u Fct When the chip is operating in standalone mode or as the master chip for parallel operation, it requires a capacitor on the CT pin ...
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... R2J20701NP Application Example Start-up Settings Case 1) Standalone or master chip in parallel operation With the RC network on the TRK-SS pin, the voltage on the pin should ramp up slowly. REG5 R TRK-SS C Case 2) Coincident tracking The TRS-SS signal for channel two is the voltage from Vout1 after division by a resistor network. Vout1 must be greater than Vout2 ...
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... R2J20701NP Case 3) Retiometric tracking The TRS-SS of channel two is tied to TRK-SS of channel 1. No cross talk is observed between the channels. REG5 R Channel 1 TRK- REG5 R Channel 1 TRK- Output voltage REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page Vout1 R1 Vout1 (nominal) = 0.6 V ( Vout2 R3 Vout2 (nominal) = 0.6 V ...
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... R2J20701NP Case 4) Current sharing or two-phase operation In the case of master–slave operation, the TRK-SS pin on the master device should be attached network for soft starts. TRK-SS pins of slave devices should be tied to the master’s TRK-SS pin. The error amplifiers on the slave devices can be disabled by pulling up the corresponding FB pins to REG5, and the slave devices do not require loop-compensation networks ...
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... R2J20701NP Output Voltage Setting The error amplifier of the device has an accurate 0.6 V reference voltage. Feedback thus leads to a voltage of about 0 the FB pin once the converter system has stabilized, so the output voltage is Vout = 0 ( Loop Compensation Peak-current control makes design in terms of phase margins easier than is the case with voltage control. This is because of differences between the characteristics of the PWM modulator and power stage in the two methods ...
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... R2J20701NP Rf Vout 0.6 V reference Figure 3 Error Amplifier Compensation Design example Specification 360 nH 600 PF, Fsw = 500 kHz, Vin = 12 V, Vout = 1 k k:, RCS = 750 : 1. Flat-band gain of error amplifier The flat-band gain is ( {R2 / (R1 + R2)} Hence }}(1) In the Bode plot, the total gain should be less than 1 (0 dB) at the switching frequency ...
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... R2J20701NP Equation ( RCS SQRT {Vin 8 L Vin 2 18500 / 750 = 2 SQRT { 360 nH 106.56 = SQRT {70.687} = 12.674 The frequency of the pole established by the power stage and modulator RCS u A0) }}(5) Thus 18500 / ( 600 PF u 750 : u 12.674) = 516 Hz Therefore, the frequency of the zero established by Cf and Rf is Fzero = ...
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... R2J20701NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB u ( }}(6) Here, the typical feedback voltage is 0 The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has a variation of 1% and resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is extended to produce equation (7) ...
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... R2J20701NP The accuracy of Vout can be estimated by using equation (10). For example, if Vout (typical) = 1.8 V, resistance variation is 1% (i.e. K1 1.01 and 0.99), and VFB = 594 mV to 606 mV: Vout VFB = Vout (typical) Vout (typical) 606 2.36% or 594 2.31% Therefore, the output accuracy will be r2.3% under the above conditions. ...
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... R2J20701NP Current Sharing Simply tie the Ishare pins together SYNC Device 1 Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare External Synchronization Simply tie the CT pin to GND External clock External clock; Frequency range: 200 kHz to 1 MHz Minimum pulse width: 100 ns Maximum pulse duty cycle: 90% REJ03G1459-0300 Rev ...
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... R2J20701NP Current Sharing and Synchronization Tie the Ishare and SYNC pins together SYNC Device 1 (Master) Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare Two-Phase Operation Tie the Ishare and SYNC pins together. SYNC Device 1 (Master) Ishare SYNC Device 2 Ishare (Slave) ...
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... R2J20701NP Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) TLD 50 ns (typ.) RAMP 0 V VIN obtain stable operation, settings should be such that the level on the switching node is high for at least 80 ns. Note: Propagation delay is ignored. ...
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... R2J20701NP Oscillator and Pulse Generator 1. Standalone operation or operation as the master chip in a parallel configuration with other chips SYNC 0 V Max. Duty (Internal signal (typ.) RES (Internal signal) Note: Propagation delay is ignored. Frequency of oscillation for CT: 160 A Fct = 2 (CT( pF) Switching frequency Fsw = 0 ...
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... R2J20701NP 2. Operation as a slave chip (simple synchronous operation) 0 SYNC (Input Max. Duty (Internal signal (typ.) RES (Internal signal) SYNC frequency range: 200 kHz to 1 MHz Note: Propagation delay is ignored. 3. Operation as a slave chip in a parallel configuration (two-phase operation) ...
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... R2J20701NP Hiccup Operation when the Over-Current Limit (OCL) is Reached TRK-SS 1 1024 pulses skipped 0 V Note: Propagation delay is ignored. REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page Detected OCL 1024 pulses skipped Normal operation ...
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... R2J20701NP Main Characteristics VH vs. Temperature 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 –50 – Temperature (°C) Vreg vs. Temperature 5.10 5.05 5.00 4.95 4.90 –50 – Temperature (°C) REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 100 125 150 –50 –25 610 608 606 604 602 600 598 596 594 592 590 100 125 150 – ...
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... R2J20701NP Fsync vs. Temperature 500 490 480 470 460 450 440 430 –50 – Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 –50 – Temperature (°C) REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 100 125 150 –50 –25 2000 1000 100 100 125 150 10 Von vs ...
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... R2J20701NP Package Dimensions JEITA Package Code RENESAS Code — PWQN0056KB REJ03G1459-0300 Rev.3.00 Jun 20, 2007 Page Previous Code MASS[Typ.] — 0.17g A B 1.00 3.40 0. 3.60 3.25 43 0.45 0.80 3. Standard Foot Print 1. ...
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Sales Strategic Planning Div. Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness ...