r2j20702np Renesas Electronics Corporation., r2j20702np Datasheet
r2j20702np
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r2j20702np Summary of contents
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... R2J20702NP Peak Current Mode Synchronous Buck Controller with Power MOS FETs Description This all-in-one SiP for POL (point-of-load) applications is a multi-chip module incorporating a high-side MOS FET, low-side MOS FET, and PWM controller in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver circuit, making this device suitable for large-current high-efficiency buck converters ...
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... R2J20702NP Application Circuit Example SYNC REG5 TRK- SGND REJ03G1782-0401 Rev.4.01 Jun 17, 2010 SW Controller Chip Target Specification VIN ( VOUT (1.8 V) Page ...
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... R2J20702NP Block Diagram REJ03G1782-0401 Rev.4.01 Jun 17, 2010 Target Specification Page ...
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... R2J20702NP Pin Arrangement VIN 15 VIN 16 VIN 17 VIN 18 VIN 19 VIN PGND 22 PGND 23 PGND 24 PGND 25 PGND 26 PGND 27 PGND Package: 56-pin QFN (8 mm Note: All die-pads (three pads in total) should be soldered to PCB. REJ03G1782-0401 Rev.4.01 Jun 17, 2010 VIN ...
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... R2J20702NP Pin Description Pin Name Pin No. VIN Input voltage for the buck converter 21 Switching node. Connect a choke coil between the SW pin and dc output node of the converter. PGND Ground of the power stage. SGND 6, 52 Ground of the IC chip. ...
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... R2J20702NP Absolute Maximum Ratings Item Power dissipation Average output current Input voltage Switch node voltage BOOT pin voltage ON/OFF pin voltage SYNC pin voltage Voltage on other pins REG5 current Ishare current TRK-SS dc current IREF current EO sink current Operating junction temperature Storage temperature Notes: 1. Pt(25) represents a PCB temperature of 25° ...
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... R2J20702NP Electrical Characteristics Item Supply VIN start threshold VIN shutdown threshold UVLO hysteresis Input bias current Input shutdown current 5-V Output voltage regulator Line regulation Load regulation 5.25-V Output voltage regulator Disable threshold Remote On/off Enable threshold Input current Reference IREF pin voltage ...
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... R2J20702NP Item Current CS current ratio sense Leading edge blanking time CS comparator delay to output OCP comparator threshold on CS pin Hiccup interval RAMP offset voltage CS offset current Note: 1. These are reference values for design and have not been 100% tested in production. REJ03G1782-0401 Rev.4.01 Jun 17, 2010 (Ta = 25° ...
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... Furthermore, if the ON/OFF pin is in the low state or left open, functioning of the IC is disabled and both MOS FETs are turned off. Relationship between FB Pin and a Pull-down MOS FET on TRK-SS Pin When R2J20702NP works as a slave module in a multi-phase power supply, FB pin should be connected to REG5 pin. In this case, the pull-down MOS FET on TRK-SS pin does not be turned on. REJ03G1782-0401 Rev.4.01 ...
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... R2J20702NP Oscillator and Pulse Generator The frequency of oscillation is set by the value of the external capacitor connected to the CT pin. This frequency is twice as high as the actual switching frequency. The frequencies are determined by the following equations: Oscillator frequency; Fct = 160 (CT( pF) Switching frequency ...
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... R2J20702NP Application Example Start-up Settings Case 1) Standalone or master chip in parallel operation With the RC network on the TRK-SS pin, the voltage on the pin should ramp up slowly. REG5 R TRK-SS C Case 2) Coincident tracking The TRS-SS signal for channel two is the voltage from Vout1 after division by a resistor network. Vout1 must be greater than Vout2 ...
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... R2J20702NP Case 3) Retiometric tracking The TRS-SS of channel two is tied to TRK-SS of channel 1. No cross talk is observed between the channels. REG5 R Channel 1 TRK- REG5 R Channel 1 TRK- Output voltage REJ03G1782-0401 Rev.4.01 Jun 17, 2010 Vout1 SW R1 Vout1 (nominal Vout2 SW R3 Vout2 (nominal) = 0.6 V ...
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... R2J20702NP Case 4) Current sharing or two-phase operation In the case of master–slave operation, the TRK-SS pin on the master device should be attached network for soft starts. TRK-SS pins of slave devices should be tied to the master’s TRK-SS pin. The error amplifiers on the slave devices can be disabled by pulling up the corresponding FB pins to REG5, and the slave devices do not require loop-compensation networks ...
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... R2J20702NP Output Voltage Setting The error amplifier of the device has an accurate 0.6 V reference voltage. Feedback thus leads to a voltage of about 0 the FB pin once the converter system has stabilized, so the output voltage is Vout = 0.6 V ( Loop Compensation Peak-current control makes design in terms of phase margins easier than is the case with voltage control. This is because of differences between the characteristics of the PWM modulator and power stage in the two methods ...
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... R2J20702NP Rf Vout Design example Specification 360 nH 600 F, Fsw = 500 kHz, Vin = 12 V, Vout = 1 k k, RCS = 750 1. Flat-band gain of error amplifier The flat-band gain is ( {R2 / (R1 + R2)} Hence Af R1 (1) In the Bode plot, the total gain should be less than 1 (0 dB) at the switching frequency ...
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... R2J20702NP Equation ( RCS SQRT {Vin 22000 / 750 = 2 SQRT { 360 nH 126.72 = SQRT {70.502} = 15.092 The frequency of the pole established by the power stage and modulator Co RCS A0) (5) Thus 22000 / (2 600 F 750 15.092) = 516 kHz Therefore, the frequency of the zero established by Cf and Rf is Fzero = 10 ...
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... R2J20702NP Study of Vout Accuracy The nominal output voltage is calculated as Vout = VFB ( (6) Here, the typical feedback voltage is 0 The accuracy of Vout is strongly dependent on the variation of VFB, R1 and R2. VFB has a variation of 1% and resistance intrinsically has a certain variation. When we take the variation in resistance into account, equation (6) is extended to produce equation (7) ...
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... R2J20702NP The accuracy of Vout can be estimated by using equation (10). For example, if Vout (typical) = 1.8 V, resistance variation is 1% (i.e. K1 1.01 and 0.99), and VFB = 594 mV to 606 mV: Vout VFB = Vout (typical) Vout (typical) 606 2.36% or 594 2.31% Therefore, the output accuracy will be 2.3% under the above conditions. ...
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... R2J20702NP Current Sharing Simply tie the Ishare pins together SYNC Device 1 Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare External Synchronization External clock External clock; Frequency range: 200 kHz to 1 MHz Minimum pulse width: 100 ns Maximum pulse duty cycle: 90% REJ03G1782-0401 Rev ...
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... R2J20702NP Current Sharing and Synchronization Tie the Ishare and SYNC pins together SYNC Device 1 (Master) Ishare SYNC Device 2 Ishare SYNC Device N ( Ishare Two-Phase Operation Tie the Ishare and SYNC pins together. SYNC Device 1 (Master) Ishare SYNC Device 2 Ishare (Slave) ...
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... R2J20702NP Timing Chart Peak Current Control Max. Duty (Internal signal) RES (Internal signal) TLD 50 ns (typ.) RAMP 0 V VIN Note: Propagation delay is ignored. REJ03G1782-0401 Rev.4.01 Jun 17, 2010 EO (EO-Vbe (Internal signal) The high-side MOS FET is turned off by the max. duty signal. ...
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... R2J20702NP Oscillator and Pulse Generator 1. Standalone operation or operation as the master chip in a parallel configuration with other chips SYNC 0 V Max. Duty (Internal signal (typ.) RES (Internal signal) Note: Propagation delay is ignored. Frequency of oscillation for CT: 160 µA Fct = ...
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... R2J20702NP 2. Operation as a slave chip (simple synchronous operation) 0 SYNC (Input Max. Duty (Internal signal (typ.) RES (Internal signal) SYNC frequency range: 200 kHz to 1 MHz Note: Propagation delay is ignored. 3. Operation as a slave chip in a parallel configuration (two-phase operation) ...
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... R2J20702NP Hiccup Operation when the Over-Current Limit (OCL) is Reached TRK-SS 1 1024 pulses skipped 0 V Note: Propagation delay is ignored. REJ03G1782-0401 Rev.4.01 Jun 17, 2010 Detected OCL 1024 pulses skipped Normal operation Target Specification Page ...
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... R2J20702NP Main Characteristics VH vs. Temperature 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 –50 – Temperature (°C) Vreg vs. Temperature 5.10 5.05 5.00 4.95 4.90 –50 – Temperature (°C) REJ03G1782-0401 Rev.4.01 Jun 17, 2010 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 75 100 125 150 –50 –25 610 608 606 604 602 600 598 596 594 592 590 75 100 125 150 –50 –25 Target Specification VL vs ...
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... R2J20702NP Fsync vs. Temperature 500 490 480 470 460 450 440 430 –50 – Temperature (°C) Voff vs. Temperature 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 –50 – Temperature (°C) REJ03G1782-0401 Rev.4.01 Jun 17, 2010 2.70 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 75 100 125 150 –50 –25 2000 1000 100 75 100 125 150 10 Target Specification Von vs ...
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... R2J20702NP Package Dimensions JEITA Package Code RENESAS Code P-HVQFN56-8x8-0.50 PVQN0056KA Index mark y Ordering Information Part Name R2J20702NP#G3 REJ03G1782-0401 Rev.4.01 Jun 17, 2010 Previous Code MASS[Typ.] — 0. Quantity 2500 pcs Target Specification 42 43 3.0 0.0 0.3 1.0 Dimension in Millimeters ...
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... Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 Notice © 2010 Renesas Electronics Corporation. All rights reserved. http://www.renesas.com Colophon 1.0 ...