a6810eep Allegro MicroSystems, Inc., a6810eep Datasheet

a6810eep

Manufacturer Part Number

a6810eep

Description

Dabic-iv, 10-bit Serial-input, Latched Source Drivers

Manufacturer

Allegro MicroSystems, Inc.

Datasheet

1.A6810EEP.pdf (8 pages)

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GROUND

STROBE

Logic Supply Voltage, V

Driver Supply Voltage, V

Continuous Output Current Range,

Input Voltage Range,

Package Power Dissipation,

Operating Temperature Range, T

Storage Temperature Range,

Caution: These CMOS devices have input

static protection (Class 2) but are still

susceptible to damage if exposed to

extremely high static electrical charges.

SUPPLY

CLOCK

LOGIC

OUT

(Suffix ‘E–’) .................. -40

(Suffix ‘S–’) .................. -20

OUT

........................................ See Graph

............................... -55

....................... -0.3 V to V

......................... -40 mA to +15 mA

CLK

LATCHES

................... 7.0 V

................... 60 V

BLNK

C to +125

C to +85

+ 0.3 V

SERIAL

DATA OUT

SERIAL

DATA IN

BLANKING

OUT

LOAD

SUPPLY

OUT

Dwg. PP-029

6809

6810

registers, accompanying data latches and control circuitry with bipolar

sourcing outputs and pnp active pull downs. Designed primarily to

drive vacuum-fluorescent displays, the 60 V and -40 mA output ratings

also allow these devices to be used in many other peripheral power

driver applications. The A6809– and A6810– feature an increased data

input rate (compared with the older UCN/UCQ5810-F) and a con-

trolled output slew rate. The A6809xLW and A6810xLW are identical

except for pinout.

microprocessor-based systems. With a 3.3 V or 5 V logic supply,

typical serial-data input rates are up to 33 MHz.

tions requiring additional drive lines. Similar devices are avail-able as

the A6811– (12 bits), A6812– (20 bits), and A6818– (32 bits).

tons, capable of sourcing up to 40 mA. The controlled output slew rate

reduces electromagnetic noise, which is an important consideration in

systems that include telecommunications and/or microprocessors and

to meet government emissions regulations. For inter-digit blanking, all

output drivers can be disabled and all sink drivers turned on with a

BLANKING input high. The pnp active pull-downs will sink at least

2.5 mA.

performance in commercial (suffix S-) or industrial (suffix E-) applica-

tions. The A6810– is provided in three package styles for through-hole

DIP (suffix -A), surface-mount SOIC (suffix -LW), or minimum-area

surface-mount PLCC (suffix -EP). The A6809– is provided in the

SOIC (suffix -LW) only. Copper lead frames, low logic-power dissi-

pation, and low output-saturation voltages allow all devices to source

25 mA from all outputs continuously over the maximum operating

temperature range.

I Controlled Output Slew Rate

I High-Speed Data Storage

I 60 V Minimum

I High Data Input Rate

I PNP Active Pull-Downs

temperature range (E- or S-) and package type (-A, -EP, or -LW).

Always order by complete part number, e.g., A6810SLW .

Output Breakdown

The A6809– and A6810– devices combine 10-bit CMOS shift

The CMOS shift register and latches allow direct interfacing with

A CMOS serial data output permits cascade connections in applica-

The A6809– and A6810– output source drivers are npn Darling-

All devices are available in two temperature ranges for optimum

Complete part number includes a suffix to identify operating

DABiC-IV, 10-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

AND

I Low Output-Saturation Voltages

I Low-Power CMOS Logic

I Improved Replacements

and Latches

for TL4810–, UCN5810–,

and UCQ5810–

Related parts for a6810eep

a6810eep Summary of contents

Page 1

OUT 1 8 OUT OUT 6 LATCHES CLK V CLOCK REGISTER 14 GROUND 5 REGISTER LATCHES LOGIC V BLNK SUPPLY STROBE OUT ...

... BLANKING 14 OUT 1 0.5 13 OUT 2 12 OUT CONNECTION Dwg. PP-029-2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 1998, 2000 Allegro MicroSystems, Inc Dwg. EP-010 CLK LATCHES REGISTER 6 16 REGISTER ...

Page 3

CLOCK SERIAL DATA IN STROBE BLANKING GROUND OUT Serial Shift Register Contents Data Clock Input Input ... N ... N ... R ...

Page 4

AND 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS Characteristic Symbol Output Leakage Current I CEX Output Voltage V OUT(1) V OUT(0) Output Pull-Down Current I OUT(0) Input Voltage V IN(1) V IN(0) Input Current I IN(1) I IN(0) Input Clamp ...

Page 5

CLOCK SERIAL DATA IN SERIAL DATA OUT STROBE BLANKING OUT BLANKING OUT A. Data Active Time Before Clock Pulse (Data Set-Up Time), t ......................................... 25 ns su(D) B. Data Active Time After Clock Pulse (Data Hold Time), t ............................................... 25 ...

Page 6

AND 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS 18 0.280 0.240 1 0.070 0.045 0.210 MAX 0.015 MIN 0.022 0.014 18 7.11 6.10 1 1.77 1.15 5.33 MAX 0.39 MIN 0.558 0.356 NOTES: 1. Exact body and lead configuration at ...

Page 7

... The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current ...

Page 8

AND 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS 20 0.2992 0.2914 0.020 0.013 0.0926 0.1043 0.0040 20 7.60 7.40 0.51 0.33 2.65 2.35 0.10 NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown. 2. Lead spacing ...

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