l9733 STMicroelectronics, l9733 Datasheet - Page 21

• Manufacturer Part Number: l9733
• Description: Octal Self Configuring Low/high Side Driver
• Manufacturer: STMicroelectronics

L9733
5.4
5.5
5.6
Table 9.
MSB
MSB
MSB
b15
b15
b15
1
1
1
b14
b14
b14
Key word
Key word
Key word
0
0
0
Serial clock (SCLK)
This is the clock signal input for synchronization of serial data transfer. DI data is shifted into
the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK.
The SCLK input has a nominal 100kΩ resistor connected from this pin to the VDO pin,
which pulls this pin to VDO if an open circuit condition occurs.
Initial input command register & fault register SPI cycle
After initial application of Vdd to the L9733, the input command register and the fault register
are "Cleared" by the POR circuitry and that means that the default condition for the output
status is Off, the default diagnostic mode is No Latch and the switching OFF overcurrent
protection is enable. During the initial SPI cycle, and all subsequent cycles, valid fault data
will be clocked out of DO (fault bits).
Input command register
An input byte (16 bits) is routed to the Command Register. The content of this Command
Register is given in table 9. Additional DI data will continue to be wrapped around to the DO
pin. If CS should happen to go high before complete reception of the current byte, this just
transmitted byte shall be ignored (invalid).
Bit command register definition
b13
b13
b13
1
1
1
b12
b12
b12
0
0
0
b11
b11
b11
Writing mode: protect
Writing mode: output
1
0
1
Writing mode: diag
b10
b10
b10
1
0
0
b9
b9
b9
0
1
1
b8
b8
b8
0
1
0
OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1
Diag 8 Diag 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1
Ilim 8 Ilim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2
b7
b7
b7
b6
b6
b6
Driver overcurrent protection
b5
b5
b5
Driver diag mode
Output status
Serial peripheral interface (SPI)
b4
b4
b4
b3
b3
b3
b2
b2
b2
b1
b1
b1
Ilim 1
LSB
LSB
LSB
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b0
b0
b0