ncv8881 ON Semiconductor, ncv8881 Datasheet - Page 26

• Manufacturer Part Number: ncv8881
• Description: Ncv8881 1.5a Automotive Buck Regulator With Watchdog
• Manufacturer: ON Semiconductor

WATCHDOG
WATCHDOG FUNCTION
that WDI pulses arrive more frequently than the
programmed minimum rate. Monitoring commences after
two sequential time periods (the POR and BOOT Delays)
which start when the SMPS output reaches regulation. After
these initial time periods, time between WDI falling edges
exceeding the Watchdog Delay indicates abnormal
microcontroller activity, and the NCV8881 responds by
pulling the open drain RESB output low. A single external
resistor from the RDLY pin to ground programs the POR,
BOOT and Watchdog Delays.
regulation, the NCV8881 enters the POR Delay period
t
POR Delay expires, the NCV8881 enters the BOOT Delay
period t
pulled up by the external resistance. When the BOOT Delay
expires, the Watchdog circuit begins monitoring the WDI
pin for a falling edge (from a microprocessor or other signal
source). If a falling edge arrives before the Watchdog Delay
period t
ENABLE
POR
5P0
SMPS
OUTPUT
8P5
The Watchdog function monitors the WDI input to check
When enabled and upon the SMPS output reaching
VIN
, during which the RESB pin is held low. When the
0
BD
Regulation Threshold
Short−Circuit Threshold
WD
during which the RESB output is allowed to be
expires, RESB remains high and a new
1
2
Figure 51. SMPS Short−Circuit After Successful Startup #2
SOFT−START TIMER
3
4
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5
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6
Watchdog Delay period is initiated. Otherwise the
NCV8881 enters another POR Delay period and the RESB
pin is pulled low, while the SMPS and LDO outputs continue
to regulate. If EN is low when the Watchdog Delay expires
(no falling edge has occurred at the WDI input), RESB is
pulled low and the NCV8881 shuts off all power outputs
(SMPS and LDOs) and minimizes supply current.
pulled low, they must never occur further apart than the
minimum specified t
to be pulled low unless pulses occur further apart than the
maximum specified t
(V
voltage low) also initiate POR and BOOT Delays prior to
resumption of WDI monitoring.
the POR, BOOT, and Watchdog Delays during start−up and
shutdown.
value proportional to the switching period in case the
resistance at the RDLY pin becomes excessively high, such
as would occur if the path from the RDLY pin through the
RDLY resistance becomes an open circuit.
In order to ensure that WDI pulses keep RESB from being
Removal of other conditions that cause RESB to go low
Figures 52 through 57 illustrate the action of RESB and
The Watchdog Delay is internally limited to a maximum
IN
> V
7
OVSTP
SMPS LATCHED OFF
, temperature > T
8
WD
WD
. However, RESB is not guaranteed
.
9
TSD
10
, and SMPS output
11
12