a4985 Allegro MicroSystems, Inc., a4985 Datasheet - Page 9

• Manufacturer Part Number: a4985
• Description: Dmos Microstepping Driver With Translator And Overcurrent Protection
• Manufacturer: Allegro MicroSystems, Inc.

A4985
turns off either the source FET (when in Slow Decay Mode) or
the sink and source FETs (when in Mixed Decay Mode).
The maximum value of current limiting is set by the selection of
R
tion is approximated by the maximum value of current limiting,
I
where R
the input voltage on the REF pin (V).
The DAC output reduces the V
comparator in precise steps, such that
(See table 2 for %I
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Low Current Microstepping.
where the minimum on-time prevents the output current from
regulating to the programmed current level at low current steps.
To prevent this, the device can be set to operate in Mixed decay
mode on both rising and falling portions of the current waveform.
This feature is implemented by shorting the ROSC pin to ground.
In this state, the off-time is internally set to 30 μs.
Fixed Off-Time.
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, t
ROSC terminal. The ROSC terminal has three settings:
▪ ROSC tied to VDD — off-time internally set to 30 μs, decay
▪ ROSC tied directly to ground — off-time internally set to
▪ ROSC through a resistor to ground — off-time is determined
Blanking.
TripMAX
Sx
mode is automatic Mixed decay except when in full step where
decay mode is set to Slow decay
30 μs, current decay is set to Mixed decay for both increasing
and decreasing currents, except in full step where decay mode
is set to Slow decay. (See Low Current Microstepping section.)
by the following formula, the decay mode is automatic Mixed
decay for all step modes.
where t
and the voltage at the VREF pin. The transconductance func-
S
(A), which is set by
is the resistance of the sense resistor (Ω) and V
OFF
This function blanks the output of the current sense
is in μs.
I
trip
TripMAX
= (%I
I
The internal PWM current control circuitry
TripMAX
t
OFF
TripMAX
at each step.)
≈ R
= V
REF
OSC
REF
/ 100)
output to the current sense
/ ( 8
Intended for applications
⁄ 825
×
OFF

I
R
TripMAX
, is determined by the
DMOS Microstepping Driver with Translator
S
)
REF
is
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, t
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protect-
ing the device from damage. In the case of a short-to-ground, the
device will remain disabled (latched) until the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ input goes
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 4.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (≈1 μs) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 5.
If the driver is operating in Mixed decay mode, it is normal for
the positive current to spike, due to the bridge going in the for-
ward direction and then in the negative direction, as a result of the
direction change implemented by the Mixed decay feature. This
is shown in figure 6. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
Charge Pump
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
V
ate the sink-side FET outputs. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. V
monitored. In the case of a fault condition, the FET outputs of the
A4985 are disabled.
REG
(VREG)
and Overcurrent Protection
.
This internally-generated voltage is used to oper-
(CP1 and CP2). The charge pump is used to
t
BLANK
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
BLANK
≈ 1 μs
(μs), is approximately
REG
is internally
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