ml4824cs-2 Fairchild Semiconductor, ml4824cs-2 Datasheet - Page 11

• Manufacturer Part Number: ml4824cs-2
• Description: Power Factor Correction And Pwm Controller Combo
• Manufacturer: Fairchild Semiconductor

LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will
be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.
REV. 1.01 12/7/2000
Figure 3. External Component Connections to V
ML4824
V BIAS
GND
V CC
R BIAS
CERAMIC
+
DC
10nF
VIN
REF
OSC
L1
I1
U4
+
–
EA
RAMP
CLK
U3
Figure 4. Typical Trailing Edge Control Scheme.
CERAMIC
1µF
SW2
SW1
+
–
U1
I2
C1
CC
I4
I3
D
R
DFF
CLK
U2
RL
Q
Q
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the first
stage is reduced. Calculation and evaluation have shown
that the 120Hz component of the PFC’s output ripple
voltage can be reduced by as much as 30% using this
method.
TYPICAL APPLICATIONS
Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
RAMP
VSW1
VEAO
TIME
TIME
ML4824
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