ml4801 Fairchild Semiconductor, ml4801 Datasheet - Page 10

• Manufacturer Part Number: ml4801
• Description: Variable Feedforward Pfc/pwm Controller Combo
• Manufacturer: Fairchild Semiconductor

ML4801
LEADING/TRAILING MODULATION
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 3 shows a typical trailing edge
control scheme.
In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 4
shows a leading edge control scheme.
10
+
DC
VIN
REF
OSC
U4
I1
L1
Figure 3. Typical Trailing Edge Control Scheme
+
–
EA
RAMP
CLK
U3
SW2
SW1
+
–
U1
I2
C1
I4
D
R
I3
DFF
CLK
U2
Q
Q
RL
RAMP
VSW1
VEAO
TIME
TIME
One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.
TYPICAL APPLICATIONS
Figure 9 is the application circuit for a complete 100W
power factor corrected power supply, designed using the
methods and general topology detailed in Application
Note 33.
+
DC
VIN
REF
OSC
U4
Figure 4. Leading/Trailing Edge Control Scheme
L1
I1
+
–
EA
RAMP
CLK
U3
SW2
SW1
VEAO
+
–
I2
C1
CMP
U1
I4
I3
D
R
DFF
CLK
U2
RL
Q
Q
RAMP
VSW1
VEAO
REV. 1.1 3/9/2001
TIME
TIME