cat64lc40 Catalyst Semiconductor, cat64lc40 Datasheet - Page 8

• Manufacturer Part Number: cat64lc40
• Description: 4k-bit Spi Serial Eeprom
• Manufacturer: Catalyst Semiconductor

CAT64LC40
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one t
clock (the last data bit) and will stay LOW until the write
cycle is complete. Then it will output a logical “1” until the
next WRITE cycle. The RDY/BSY output is not affected
by the input of CS.
An alternative to get RDY/BSY status is from the DO pin.
During a write cycle, asserting a LOW input to the CS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical “1” when
Figure 6. RESET During BUSY
Figure 7. EWEN Instruction Timing
Doc. No. 1021, Rev. A
RDY/BUSY
RESET
RDY/BUSY
* Please check instruction set table for address
DO
SK
CS
RESET
DI
DO
CS
SK
DI
1
SV
1
after the rising edge of the 32nd
0
0
1
BUSY
BUSY
BUSY
BUSY Instruction Timing
1
0
HIGH-Z
0
HIGH
0
0
0
1
1
0
1
0
ADDRESS*
8
the device is deselected. The rising edge of the first “1”
input on the DI pin will reset DO back to the high
impedance state again.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
NOTE: Data may be corrupted if a RESET occurs while
the device is BUSY. If the reset occurs before the BUSY
period, no writing will be initiated. However, if RESET
occurs after the BUSY period, new data will have been
written over the old data.
D15
D0
t WR
Characteristics subject to change without notice
© 2006 by Catalyst Semiconductor, Inc.
5064 FHD F09