cat64lc10 Catalyst Semiconductor, cat64lc10 Datasheet - Page 7

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cat64lc10

Manufacturer Part Number
cat64lc10
Description
1k/2k/4k-bit Spi Serial Eeprom
Manufacturer
Catalyst Semiconductor
Datasheet
a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC10/20/40 requires an active LOW CS in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of CS before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
RDY/BUSY
RDY/BUSY
RESET
RESET
DO
CS
SK
* Please check instruction set table for address
DO
DI
CS
SK
DI
WRITE INSTRUCTION
BUSY
BUSY
BUSY
BUSY
BUSY
1
0
HIGH
LOW
1
0
0
1
0
0
ADDRESS*
7
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
D15
D0
NEXT INSTRUCTION
Doc. No. 1021, Rev. C
PD
after

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