cat6095 ON Semiconductor, cat6095 Datasheet - Page 6

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cat6095

Manufacturer Part Number
cat6095
Description
Digital Output Temperature Sensor
Manufacturer
ON Semiconductor
Datasheet
CAT6095
2
I
C/SMBUS PROTOCOL
2
The I
C/SMBus uses two ‘wires’, one for clock (SCL)
and one for data (SDA). The two wires are
connected to the V
supply via pull-up resistors.
CC
Master and Slave devices connect to the bus via
their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
During data transfer, the SDA line must remain
stable while the SCL line is HIGH. An SDA transition
while SCL is HIGH will be interpreted as a START or
STOP condition (Figure 1).
START
The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all Slaves. Absent a START, a Slave will not
respond to commands.
STOP
The STOP condition completes all commands. It
consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP tells the Slave that no more
data will be written to or read from the Slave.
DEVICE ADDRESSING
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address (the preamble) select either the Temperature
Sensor (TS preamble = 0011) or some other device
sharing the bus, as shown in Figure 2. The next 3 bits,
A2, A1 and A0, select one of 8 possible TS Slave
devices. The last bit, R/W ¯ ¯ , specifies whether a Read
(1) or Write (0) operation is being performed
ACKNOWLEDGE
A matching Slave address is acknowledged (ACK)
by the Slave by pulling down the SDA line during the
th
9
clock cycle (Figure 3). After that, the Slave will
acknowledge all data bytes sent to the bus by the
Master. When the Slave is the transmitter, the
th
Master will in turn acknowledge data bytes in the 9
clock cycle. The Slave will stop transmitting after the
Master
does
not
respond
with
acknowledge
(NoACK) and then issues a STOP. Bus timing is
illustrated in Figure 4.
6
Doc. No. MD-1124 Rev. B
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice

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