lx64eb Lattice Semiconductor Corp., lx64eb Datasheet - Page 30
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lx64eb
Manufacturer Part Number
lx64eb
Description
High Performance Interfacing And Switching
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.LX64EB.pdf
(72 pages)
- Current page: 30 of 72
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Lattice Semiconductor
Figure 19. ispGDX2 Timing Model Diagram (with sysHSI and FIFO Receive Mode)
Figure 20. ispGDX2 Timing Model Diagram (with sysHSI Transmit Mode)
(Global RESET)
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
from I/O Cell
(I/O RESET)
(SSCLKIN)
(REFCLK)
(Control)
(SIN)
t
t
t
HSICTRLCAL
HSISSCLKIN
HSIREFCLK
t
HSISIN
t
HSIFIFORST
from I/O Cell
from I/O Cell
(REFCLK)
HSI Controls
(TXD)
Serial Data
In
CAL
Source
Synchronous Clock
Reference Clock
sysHSI
(RXD)
RESET
t
t
HSITXDATA
HSIREFCLK
HSI Flags
Recovered
CSLOCK
Data Out
(RXD)
SYDT
Clock
Data In
Reference Clock
from I/O Cell
from I/O Cell
(RCLK)
(RE)
(Output Path Flag)
(SYDT and Output
Path Flags)
to I/O Cell
to I/O Cell
30
t
t
FIFODATAIN
FIFOWCLK
sysHSI
(TXD)
Synchronous Clock
t
t
FIFORCLK
FIFOREN
Data Out
Source
Serial
Write CLK
Read
Clock
Read
Enable
Data In
RESET
ispGDX2 Family Data Sheet
FIFO
to I/O Cell
(SSCLKOUT)
(SOUT)
to I/O Cell
FULL, EMPTY
FIFO Flags
Data Out
(Output Path Flags)
(RECCLK)
to I/O Cell
to I/O Cell
(DOUT)
to I/O Cell
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