ncv4279a ON Semiconductor, ncv4279a Datasheet - Page 10

• Manufacturer Part Number: ncv4279a
• Description: 5.0 V Micropower 150 Ma Ldo Linear Regulator With Delay, Adjustable Reset, And Sense Output
• Manufacturer: ON Semiconductor

OUTPUT REGULATOR
The PNP output has drive quiescent current control for
regulation while the input voltage is low, preventing over
saturation. Current limit and voltage monitors complement
the regulator design to give safe operating signals to the
processor and control circuits.
RESET OUTPUT (RO)
generated as the IC powers up. After the output voltage V
increases above the reset threshold voltage V
timer D is started. When the voltage on the delay timer V
passes V
the delay timer V
the reset threshold voltage V
delay timer V
the reset output voltage V
processor.
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
guaranteeing that RO is valid for V
RESET ADJUST (R
value of 4.65 V to as low as 3.5 V by using an external
voltage divider connected from the Q lead to the pin RADJ,
as shown in Figure 18. The resistor divider keeps the voltage
above the V
voltages, and overrides the internal threshold detector.
Adjust the voltage divider according to the following
relationship:
V RT + V RADJ, TH @ (R ADJ1 ) R ADJ2 ) R ADJ2
The output is controlled by a precision trimmed reference.
A reset signal, Reset Output, RO, (low voltage) is
The reset output RO is an open collector NPN transistor,
The reset threshold V
V
BAT
UD
C
C
, the reset signal RO goes high. A discharge of
I
D
*
RADJ,TH
D
drops below the lower threshold voltage V
D
is started when V
0.1 mF
ADJ
(typical 1.35 V) for the desired input
*C
** C
pected. Cap must operate at required temperature range.
I
)
RT
required if regulator is located far from the power supply filter.
Q
− minimum cap required for stability is 2.2 mF while higher over/under−shoots may be ex-
can be decreased from a typical
RO
I
D
SO
RT
is brought low to reset the
. When the voltage of the
NCV4279A
Q
Q
GND
drops and stays below
as low as 1.0 V.
APPLICATION DESCRIPTION
Figure 18. Application Diagram
RT
R
, the delay
ADJ
RO
SI
Q
(eq. 1)
http://onsemi.com
LD
Q
D
R
R
ADJ1
ADJ2
10
should be connected to GND causing the reset threshold to
go to its default value (typically 4.65 V).
RESET DELAY (D)
capacitor C
provides charge current I
external delay capacitor C
SETTING THE DELAY TIME
charge current I
capacitor voltage charging from the low level of V
the higher level V
Example:
Using C
Use the typical value for V
Use the typical value for V
Use the typical value for Delay Charge Current I
If the reset adjust option is not needed, the R
The reset delay circuit provides a delay (programmable by
The delay time is set by the delay capacitor C
1. During Powerup (once the regulation threshold has
2. After a reset event has occurred and the device is
been exceeded).
back in regulation. The delay capacitor is set to
discharge when the regulation (V
threshold voltage) has been violated. When the
delay capacitor discharges to V
RO pulls low.
R
R
D
t d + [100 nF (1.8 * 0.1 V)] 6.5 mA + 26.2 ms (eq. 3)
R
SI1
SI2
RO
= 100 nF.
D
) on the reset output lead RO. The delay lead D
t d + [C D (V UD * V D, SAT )] I D
R
D
UD
SO
. The time is measured by the delay
. The time delay follows the equation:
C
10 mF
(2.2 mF)
Q
**
D
D,SAT
UD
D,C
during the following times:
= 1.8 V.
V
I/O
(typically 6.5 mA) to the
DD
= 0.1 V.
I/O
LD
RT
, the reset signal
, reset
D
D
= 6.5 mA.
DSAT
ADJ
and the
(eq. 2)
pin
to