a8292 Allegro MicroSystems, Inc., a8292 Datasheet - Page 9

• Manufacturer Part Number: a8292
• Description: Dual Lnb Supply And Control Voltage Regulator
• Manufacturer: Allegro MicroSystems, Inc.

A8292
TDET is set in the status register. When the internal tone is used
(options 1 or 2), the minimum tone detect amplitude is 400 mV,
and when an external tone is used (options 3 or 4), the minimum
tone detection amplitude is 300 mV.
I
This is a serial interface that uses two bus lines, SCL and SDA,
to access the internal Control and Status registers of the A8292.
Data is exchanged between a microcontroller (master) and the
A8292 (slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain output,
depending on the direction of the data.
Timing Considerations
The control sequence of the communication through the I
2
C™-Compatible Interface
With any of the four options, when a tone signal is generated,
Figure 2. I
SDA
SCL
Start
2
C™ Interface. Read and write sequences.
0
1
0
2
SDA
SCL
SDA
SCL
0
3
Start
Start
Address
1
4
Dual LNB Supply and Control Voltage Regulator
0
1
0
1
0
5
A1
0
2
0
2
6
A0
Read Multiple Bytes from Register
0
3
0
3
7
Address
Address
Read One Byte from Register
R
1
4
1
4
1
8
AK
0
5
0
5
9
acknowledge
from LNBR
A1
A1
D7
6
6
Write to Register
A0
A0
D6
7
7
2
Status Data in Register 1
C™-
D5
W
R
0
8
1
8
AK
AK
D4
9
9
acknowledge
from LNBR
acknowledge
from LNBR
compatible interface is composed of several steps in sequence:
1. Start Condition. Defined by a negative edge on the SDA line,
2. Address Cycle. 7 bits of address, plus 1 bit to indicate read (1)
3. Data Cycles.
D7
D3
I1
while SCL is high.
or write (0), and an acknowledge bit. The first five bits of the
address are fixed as: 00010. The four optional addresses, de-
fined by the remaining two bits, are selected by the ADD input.
The address is transmitted MSB first.
Write – 6 bits of data and 2 bits for addressing four internal
control registers, followed by an acknowledge bit. See Control
Register section for more information.
Read – Two status registers, where register 1 is read first,
followed by register 2, then register 1, and so on. At the start
of any read sequence, register 1 is always read first. Data is
transmitted MSB first.
D6
D2
I0
D5
D5
D1
Status Register 1
Control Data
D4
D4
D0
D3
D3
AK
acknowledge
from LNBR
D2
D2
-
D1
D1
-
Status Data in Register 2
D0
D0
-
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
NAK
AK
-
acknowledge
from LNBR
no acknowledge
from master
Stop
Stop
D3
D2
D1
D0
NAK
no acknowledge
from master
Stop
9