l6706 STMicroelectronics, l6706 Datasheet
l6706
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... Feedback disconnection prevents from damaging the load in case of disconnections in the system board. In case of over-current, the system works in constant current mode until UVP. Package VFQFPN-40 Doc ID 15698 Rev 1 L6706 Packing Tray Tape and reel 1/47 www.st.com 47 ...
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... DAC and current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Differential remote voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 Offset (optional 8.2 Droop function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Droop thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Output current monitoring (IMON Load transient boost technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 Dynamic VID transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 Enable and disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/47 Doc ID 15698 Rev 1 L6706 ...
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... Feedback disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 17 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 18 System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 20 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 20.1 Power components and connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 20.2 Small signal components and connections . . . . . . . . . . . . . . . . . . . . . . . 43 20.3 Embedding L6706 - Based Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Doc ID 15698 Rev 1 Contents 3/47 ...
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... Principle application circuit Figure 1. Principle application circuit V = 12V IN GND Optional:Pre-OVP V To Vcc R SSOSC Optional: D See DS 10k VTT 1k SS_END To Enable circuitry L6706 REF.SCH a. Refer to the application note for the reference schematic. 4/47 ( VCCDR 40 BOOT 37 PGND 1 39 DGND UGATE 3 38 VCC cc PHASE LGATE 36 2 ...
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... VID2 VID3 VID4 VID5 VID6 VID7 Principle application circuit and block diagram LOGIC PWM ADAPTIVE ANTI CROSS CONDUCTION PWM LTB SSOSC L6706 CONTROL LOGIC OUTEN AND PROTECTIONS DELIVERED CURRENT VREF GND DROP ERROR RECOVERY AMPLIFIER Doc ID 15698 Rev 1 +.1240V PWM1 INFO ...
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... Connect to the negative side of the load to perform remote sense. guidelines” Section for proper layout of this connection. Doc ID 15698 Rev VID0 19 INT1 18 CS- CS+ 17 OUTEN 16 15 SSOSC/FLIMIT 14 OSC/FAULT 13 OCSET OVPSEL 12 OFFSET Description - C //C vs. COMP pin for details. See “Layout See “Layout L6706 ...
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... L6706 Table 2. Pin description (continued) N° Name 8 LTB 9 IMON 10 LTBGAIN 11 OFFSET 12 OVPSEL 13 OCSET OSC/ 14 FAULT SSOSC/ 15 FLIMIT Pins description and connection diagrams Load transient boost pin. Internally fixed connecting a R load transient boost technology™: as soon as the device detects a transient load it turns on the PHASE. Short to SGND to disable the transient boost technology” ...
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... A small series resistor helps in reducing device-dissipated power. Power ground pin (LS drivers return path). Connect to power ground plane. HS driver return path. It must be connected to the HS MOSFET source and provides return path for the HS driver. Doc ID 15698 Rev 1 Description for proper layout of this for proper layout of this L6706 Table 7. ...
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... L6706 Table 2. Pin description (continued) N° Name 39 UGATE 40 BOOT Thermal PAD PAD 2.2 Thermal data Table 3. Thermal data Symbol Thermal resistance junction to ambient R thJA (Device soldered on 2s2p PC board) R Thermal resistance junction to case thJC T Maximum junction temperature MAX T Storage temperature range stg T Junction temperature range ...
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... LGATE = OPEN, VCCDR = 12 V UGATE = OPEN, PHASE to PGND; VCC = BOOT = 12 V VCC rising; VCCDR = VCC VCC falling; VCCDR = VCC OSC = OPEN OSC = OPEN 125 ° kΩ SSOSC Doc ID 15698 Rev 1 L6706 Value Unit -0.3 to Vcc+0.3 V -0.3 to 3.6 V ...
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... L6706 Table 5. Electrical characteristics (continued) Symbol Parameter time 3 3 Output enable OUTEN Output pull-up current ΔVosc Ramp amplitude FAULT Voltage at pin OSC/FAULT Reference and DAC K Output voltage accuracy VID V Boot voltage BOOT VID IH VID thresholds VID IL Error amplifier gain ...
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... Above VID (after OVP = SGND OVP = 1.800 V UVLO < VCC < UVLO OVP VCC VCC> UVLO and OUTEN = SGND VCC VSEN rising Hysteresis VSEN falling; below VID Doc ID 15698 Rev 1 L6706 Min. Typ. Max. Unit 1.24 1.300 V 150 175 200 mV μ -20 0 ...
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... L6706 4 Voltage identifications Table 6. Voltage Identification (VID) mapping Intel VR11.x VID7 VID6 800 mV 400 mV Table 7. Voltage Identification (VID) Intel VR11.x Output HEX code voltage 0 0 OFF 0 1 OFF 0 2 1.60000 0 3 1.59375 0 4 1.58750 0 5 1.58125 0 6 1.57500 0 7 1.56875 0 8 1.56250 ...
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... F 0.51875 E F 0.11875 0 0.51250 F 0 0.11250 1 0.50625 F 1 0.10625 2 0.50000 F 2 0.10000 3 0.49375 F 3 0.09375 4 0.48750 F 4 0.08750 5 0.48125 F 5 0.08125 6 0.47500 F 6 0.07500 7 0.46875 F 7 0.06875 8 0.46250 F 8 0.06250 9 0.45625 F 9 0.05625 A 0.45000 F A 0.05000 B 0.44375 F B 0.04375 L6706 (1) ...
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... L6706 Table 7. Voltage Identification (VID) Intel VR11.x Output HEX code voltage 3 C 1.23750 3 D 1.23125 3 E 1.22500 3 F 1.21875 1. According to INTEL specs, the device automatically regulates output voltage 19 mV lower to avoid any external offset to modify the built-in 0.5% accuracy improving TOB performances. Output regulated voltage is than what extracted from the table lowered ...
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... LTB Technology™ can be disabled and in this condition the device works as a dual-edge asynchronous PWM. L6706 permits easy system design by allowing current reading across inductor in fully differential mode. Also a sense resistor in series to the inductor can be considered to improve reading precision. ...
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... The DAC output is delivered to an amplifier obtaining the voltage reference (i.e. the set-point of the error amplifier, V L6706 embeds a flexible, fully-differential current sense circuitry that is able to read across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows placing sensing element in different locations without affecting the measurement's accuracy ...
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... MAX Where I is the maximum output current, DCR OUT 18/47 DCR ⋅ ⇒ ⋅ ------------ - CS- PHASE Rg MAX DCR ⋅ ------------------------ 20μA Doc ID 15698 Rev 1 DCR ⇒ ⋅ ------------ - INFO INFO PHASE Rg MAX OUT MAX the maximum inductor DCR. L6706 ...
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... L6706 7 Differential remote voltage sensing The output voltage is sensed in fully-differential mode between the FB and FBG pin. The FB pin has to be connected through a resistor to the regulation point while the FBG pin has to be connected directly to the remote sense ground point. In this way, the output voltage programmed is regulated between the remote sense point compensating motherboard or connector losses ...
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... Figure Doc ID 15698 Rev 1 Figure – OUT OFFSET ⋅ OUT ESR Drop V MAX V NOM V MIN RESPONSE WITHOUT DROOP RESPONSE WITH DROOP ) for the output voltage by OS Figure 7; this offset has current is programmed by 7. Output voltage is then L6706 = PROG ...
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... L6706 where: Offset resistor can be designed by considering the following relationship (RFB is fixed by the Droop effect): Offset automatically given by the DAC selection differs from the offset implemented through the OFFSET pin: the built-in feature is trimmed in production and assures ±0.5% error over load and line variations Figure 7 ...
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... Voltage positioning “real” voltage generator with an equivalent output resistance resistor can be also designed according to the R PROG FB 22/47 Rg ⋅ ------------ - = FB DROOP DCR Doc ID 15698 Rev 1 L6706 and a voltage value of DROOP specifications as follow: DROOP ...
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... L6706 9 Droop thermal compensation Current sense element (DCR inductor) has a non-negligible temperature variation consequence, the sensed current is subjected to a measurement error that causes the regulated output voltage to vary accordingly (when droop function is implemented). To recover from this temperature related error, NTC resistor can be added into feedback ...
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... IMON DROOP Doc ID 15698 Rev ⋅ ----------------------------------- + V DROOP REF IMON OS ⋅ OUT I DROOP IMON +3V3 R IMON_OS C IMON To CPU IMON NTC To GND_core R1 (Remote Sense) ⋅ ----------------------------------- DCR IMON OS ⋅ ⋅ ------------ - I = OUT IMON OS and the I , the voltage results: OUT L6706 ...
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... L6706 where T is the temperature. If the inductor temperature increases the DCR inductor increases and NTC resistor decreases consequence the equivalent R the monitoring voltage respect to temperature variation. NTC resistor must be placed as close as possible to the sense element (phase inductor). R IMON [ ] --------------------------------------------- - ...
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... After detecting a load transient, the LTB ramp is reset and LTB - C is design according to the output voltage deviation dV LTB LTB dV OUT R = ----------------- - C LTB LTB 25μA Doc ID 15698 Rev 1 Figure 10 OUT ESR C O PROG LTBGAIN R LTBGAIN LT Detect R C LTB LTB Z ( ---------------------------------------- - ⋅ ⋅ 2π LTB SW L6706 11) OUT ...
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... L6706 ● Gain design. Through the LTBGAIN pin it is possible to modify the slope of the LTB Ramp in order to modulate the entity of the LTB response once the LT has been detected. In fact, the response depends on the board design and its parasites requiring different actions from the controller. ...
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... L6706 checks for VID code modifications (see additional DVID-clock and waits for a confirmation on the following falling edge. Once the new code is stable, on the next rising edge, the reference starts stepping up or down in LSB increments every VID-clock cycle until the new VID code is reached. During the transition, VID code changes are ignored ...
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... L6706 Figure 12. Dynamic VID transitions VID Clock VID [0,7] Int. Reference T V out DVID Step VID Transition Vout Slope Controlled by internal DVID-Clock Oscillator Doc ID 15698 Rev 1 Dynamic VID transitions VID Step VID Transition Vout Slope Controlled by external driving circuit (T ...
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... Enable and disable 13 Enable and disable L6706 has three different supplies: VCC pin to supply the internal control logic, VCCDR to supply the low side driver and BOOT to supply the high side driver. If the voltage at pin VCC is not above the turn on threshold specified in the Electrical characteristics table (see keep the MOSFETs off to show high impedance to the load ...
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... Protections are active during soft-start: Under voltage is enabled when the reference voltage reaches 0.6 V while over voltage is always enabled. Figure 13. Soft-start Once L6706 receives all the correct supplies and enables, it initiates the soft-start phase with 1.5 ms (typ) delay. After that, the reference ramps ...
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... Q Soft Start time depends on selected FLIMIT 1.24 V – V – 3 DIODE ⋅ ---------------------------------------------- - 1. ⋅ ( ----------------- - DIODE BOOT V ⋅ ----------------- - DIODE BOOT and R SS SSOSC , diode versus SSEND SSOSC BJT [ ] 1.24 V – ⋅ ---------------------------------------------- - ] 1.24 L6706 > BOOT < BOOT the resistor ...
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... Figure 16. Soft-start time (T 14.1 Low-side-less startup In order to avoid any kind of negative undershoot on the load side during startup, L6706 performs a special sequence in enabling LS driver to switch: during the soft-start phase, the LS driver results disabled (LS = OFF) until the HS starts to switch. This avoid the dangerous negative spike on the output voltage that can happen if starting over a pre-biased output ...
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... Output voltage monitor and protections 15 Output voltage monitor and protections L6706 monitors through pin VSEN the regulated voltage in order to manage the OVP and UVP conditions. Protections are active also during soft-start they are masked during D-VID transitions with an additional 67µs delay after the transition has finished to avoid false triggering ...
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... L6706 15.3 Over voltage and programmable OVP Once VCC crosses the turn-ON threshold and the device is enabled (OUTEN = 1), L6706 provides an over voltage protection: when the voltage sensed by VSEN overcomes the OVP threshold (OVP TH – Permanently turns OFF the high-side MOSFETs. – Permanently turns ON the low-side MOSFET in order to protect the load. ...
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... I OCTH ( ) 1.260 typ = ---------------------------- R OCSET ΔIL ⎛ ⎞ OCP I + -------- - ⎝ ⎠ OUT 2 crossing will OCTH re-cross the threshold INFO value and this will represent the OCP OCSET design: OCSET ( ) MIN ΔIL ⎞ OCP 77μA + -------- - + ⎠ 2 L6706 externally OCSET ...
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... L6706 15.5 Feedback disconnection L6706 allows to protect the load from dangerous over voltage also in case of feedback disconnection. The device is able to recognize both FB pin and FBG pin disconnections, as shown in the Figure When VSEN pin is more than 500 mV higher then VPROG, the device recognize a FBG disconnections ...
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... R kΩ OSC vs. switching frequency Doc ID 15698 Rev 1 = 200 kHz connected between the OSC/FAULT OSC 3 ⋅ 12.40 10 ⇒ kΩ = ----------------------------------------------------------- - ) ( ) 200 kHz OSC F kHz – ⋅ 10.76 10 ⇒ kΩ = ----------------------------------------------------------- - ) OSC ( ) F 200 kHz – SW L6706 kΩ kΩ kHz ...
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... L6706 17 Driver section The integrated high-current driver allow using different types of power MOS (also multiple MOS to reduce the equivalent R The driver for the high-side MOSFETs use BOOT pin for supply and PHASE pin for return. The driver for the low-side MOSFETs use VCCDR pin for supply and PGND pin for return. A minimum voltage at VCCDR pin is required to start operations of the device ...
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... DROOP ⎛ ⎞ ⋅ 1 -------------- + + ----------- - ⎝ ⎠ the oscillator ramp amplitude OSC ⋅ ⋅ //R + ESR O DROOP O ⋅ ------------------------------------------------------------------------------------------------------------------------------- - 2 L ⋅ ⋅ ⋅ ⋅ ⋅ ESR -------- - + + R O L6706 sourced ...
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... L6706 desired crossover frequency ω zero and two poles; both the poles are fixed once the output filter is designed (LC filter resonance ω ) and the zero (ω LC Figure 24. Equivalent control loop block diagram (left) and bode diagram (right) VREF ( ...
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... Power dissipation 19 Power dissipation L6706 embeds high current MOSFET drivers for both high side and low side MOSFETs then important to consider the power the device is going to dissipate in driving them in order to avoid overcoming the maximum junction operative temperature. Exposed pad needs to be soldered to the PCB power ground plane through several VIAs in order to facilitate the heat dissipation ...
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... Two kind of critical components and connections have to be considered when layouting a VRM based on L6706: power components and connections and small signal components connections. 20.1 ...
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... Embedding L6706 - Based VR When embedding the VRD into the application, additional care must be taken since the whole VRD is a switching DC/DC regulator and the most common system in which it has to work is a digital system such similar. In fact, latest MB has become faster and powerful: high speed data bus are more and more common and switching-induced noise produced by the VRD can affect data integrity if not following additional layout guidelines ...
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... L6706 21 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. Table 9. VFQFPN-40 mechanical data Dim. ...
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... Revision history 22 Revision history Table 10. Document revision history Date 26-May-2009 46/47 Revision 1 First release Doc ID 15698 Rev 1 L6706 Changes ...
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... L6706 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...