l5953 STMicroelectronics, l5953 Datasheet

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l5953

Manufacturer Part Number
l5953
Description
Multiple Switching Voltage Regulator
Manufacturer
STMicroelectronics
Datasheet

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Features
SPI functions
Table 1.
September 2007
PWM: adjustable 2.5/10V - 1A switching
voltage regulator
External POWER MOS ability for output
current enhancement
Synchronization function
REG1- Linear low drop 3.3/5V - 250mA STBY
voltage regulator (low current consumption)
with RESET
REG2- Linear voltage regulator 1.5V to 3.3V
externally adjustable - 300mA maximum
current
HSD1 : 500mA High side driver
HSD2 : 200mA High side driver
SPI Interface
SPI Diagnostics HSD1, HSD2
Double switching frequency SPI selectable
Double inpuT LVW
Input controls
– Turn-on/off PWM
– Turn-on/off REG2
– Turn-on/off HSD1
– Turn-on/off HSD2
– Switching frequency selection f1- f2
Output functions:
– HSD1 & HSD2 short to gnd, open load and
– Thermal warning
short to battery (Test mode)
Part number
Device summary
L5953
PowerSO36
Package
Multiple switching voltage regulator
Rev 2
Protections
Description
The L5953 is the integration of one switching
regulator, two linear voltage regulators, two low
voltage warnings and two high side drivers. It has
a stand-by operation mode (low current
consumption) where only the stand-by voltage
regulator plus the low voltage warnings are active.
The other regulators and high side drivers are
controlled by the SPI interface.
Over voltage protection
Internal current limiting
Thermal shutdown
ESD
PowerSO36
Packing
Tray
L5953
www.st.com
1/31
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l5953 Summary of contents

Page 1

... Thermal shutdown ■ ESD Description The L5953 is the integration of one switching regulator, two linear voltage regulators, two low voltage warnings and two high side drivers. It has a stand-by operation mode (low current consumption) where only the stand-by voltage regulator plus the low voltage warnings are active. ...

Page 2

... Write Enable (WREN and Write Disable (WRDI Summary of the main operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 Operation 5.2 Operation 5.3 Operation 5.4 Operation 5.5 Operation 5.6 Operation 5.7 Operation 5.8 Operation 5.9 IRQ - Interrupt Request Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 REG1 output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.2 Feedback resistors for REG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/31 Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . 15 L5953 ...

Page 3

... L5953 6.3 External components for PWM regulator . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 6.3.2 6.3.3 6.4 Free-wheeling diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 Compensation Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contents 3/31 ...

Page 4

... Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Thermal data Table 4. PIN function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Diagnostic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 8. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Status register Table 10. Status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. Diagnostic register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 12. Diagnostic register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/31 L5953 ...

Page 5

... L5953 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. PIN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4. SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. Low voltage warning block diagram Figure 10. HSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. ...

Page 6

... STEP DOWN REGULATOR 2.5-10V/1A OSCILLATOR & SYNC D01AU1330A VIN SYNC DGND Value -0 -0 Internally limited From 0 - -55 to 150 -40 to 150 Value 1.7 L5953 FGND VSTBY ADJ STRAP DRAINOUT VSW GATEIN GATEOUT FB COMP SWGND GND Unit °C °C ° ...

Page 7

... L5953 Figure 2. PIN connections Table 4. PIN function Pin number 1 FGND RES DGND 13 IRQ 14 HSD2 15 VDD-LIN 16 N.C. 17 HSD1 18 SWGND 19 VDD-SW 20 DRAINOUT Block diagram and electrical specifications 1 FGND RES 6 CT ...

Page 8

... fixed at high/low logic level = 5V; unless otherwise specified 200mA 200mA 0. 0.5A 1A L5953 Function Min. Typ. Max. Unit μA 100 150 °C 2.4 2.5 2.6 V 9.6 10 10.4 V 1.275 100 0 1.2 A ...

Page 9

... L5953 Table 5. Electrical characteristics (continued) (T Symbol Parameter h Efficiency SVR Supply voltage ripple rejection Oscillator f Switching frequency 1 f Switching frequency 2 Δf Voltage stability of switching -------- - ΔV frequency i Δf Temperature stability of switching -------- - ΔT frequency j Sync V Low input voltage IL V High input voltage IH V Low output voltage ...

Page 10

... V ≤ 3. 3.3Vdc, 0.5Vacpp, 300Hz IN = 150mA; 1.5V ≤ V ≤ 0. 0. 1mA o ≥ 1mA o L5953 Min. Typ. Max. Unit 3.135 1.275 V 400 350 mV 600 mA 100 mH 300 mV 300 mA ...

Page 11

... L5953 Table 5. Electrical characteristics (continued) (T Symbol Parameter I Reset output leakage RH V Delay comparator threshold CTth Delay comparator threshold V CThy hysteresis Timing capacitor output source I CT1 current Timing capacitor output pull-down R CT2 equivalent resistor Table 6. Diagnostic parameters Symbol Parameter High side driver 1 overcurrent ...

Page 12

... Min. Max. 5 ±2 0.3V SP -0 SPI SPI 0.2V SPI 0.8V SPI 50 50 200 300 < 5.5V 200 SPI < 4.5V 250 150 250 0 100 100 0.7V SPY 0.3V SPY D03AU1479 L5953 Unit μA μ μs μ μs μ ...

Page 13

... L5953 Figure 4. SPI clocking scheme S (MODE 0: CPOL=0,CPHA= (MODE 3: CPOL=1,CPHA= Figure 5. Output timing ADDR.LSB IN D Figure 6. Serial input timing S C tDVCH D Q Block diagram and electrical specifications MSB tCLQX tQVCL MSB OUT MSB-1 OUT (CPOL=0, CPHA=0) ...

Page 14

... High side drivers Two high-side driver L5953. They are protected against short to ground: the short circuit protection limits the maximum output current. A diagnostic procedure is available to detect open load, short to battery and overcurrent. Open load and short to battery can be reveal only in test mode while overcurrent is active only during normal operation of the device ...

Page 15

... The error amplifier (EA voltage amplifier whose non-inverting input is fixed to the reference voltage (1.275V bandgap voltage) and whose inverting input and output are externally available for feedback and frequency compensation. 11.) inside the L5953 is a voltage control mode (also known (Figure Functional description ...

Page 16

... Low voltage warning block diagram. 16/31 V REF POWER MOS 1.275V V STBY V STBY CONTROLLER LINEAR REGULATOR CONTROLLER POWER MOS V REF 1.275V D03AU1493 Vref 2.5V/1.65V 7.5μA FROM VST-BY Vref 1.275V D03AU1480 V1 Vref =1.275V + Vref =1.275V + S2 - D03AU1478 L5953 STCAP VSTBY ADJ FGND FBLR VLR VIN RES ...

Page 17

... L5953 Figure 10. HSD Figure 11. PWM Figure 12. SPI & IRQ HSD1 CONTROLLER HSD2 CONTROLLER ERROR AMPLIFIER CURRENT SENSING VREF 1.275V PWM CONTROLLER FROM THE OSCILLATOR SPI INTERFACE Internal pin connections HSD1 POWER MOS HSD1 VDD-LIN POWER MOS HSD2 HSD2 D01AU1333 STRAP COMP ...

Page 18

... Q pin changes after the falling edge of the clock input. Chip select (S). This input is used to select the L5953. The chip is selected by a high to low transition on the S pin. At any time, the chip is deselected by a low to high transition on the S pin ...

Page 19

... L5953 . Table 8. Instruction set Instruction WREN WRDI WSTA RDIA RSTA . Table 9. Status register s15 s14 s13 s12 s11 REG HSD HSD TBD TBD Table 10. Status register description REG2 linear voltage s15 regulator 1.5 to 3.3V s14 High side driver 1 s13 High side driver 2 ...

Page 20

... If d7=1: bit value meaningless If d7=0: bit value meaningless HSD2W2 If d7=1: HSD2 in normal condition If d7=0: bit value meaningless HSD1W3 If d7=1: HSD2 in normal condition; Thermal warning Normal condition L5953 HSD2W2 HSD2W3 THW 0 1 The diagnostic register is referred to a test performed in Test mode If d7=0: HSD1 is in overcurrent If d7=1: bit value ...

Page 21

... L5953 5 Summary of the main operations 5.1 Operation A ● Test mode diagnostic procedure start ● 1) WREN instruction ● 2) WSTA instruction 5.2 Operation B ● Read the diagnostic register Case1: after a test mode diagnostic procedure start 1) RDIA instruction 2) Diagnostic register output Note: An operation B must follow an operation A. The delay between the end of the operations A to the start of the operations B must be longer than 100 5 ...

Page 22

... HIGH IMPEDANCE CPOL=0, CPHA INSTRUCTION DIAGNOSTIC REGISTER OUT D03AU1483 STATUS REGISTER s11 s10 L5953 D03AU1484 D03AU1485 ...

Page 23

... L5953 Figure 16. Diagnostic procedure start (after write enable latch sequence operation Figure 17. Read the diagnostic RegisterCase2: during the normal working of the L5953 (after a diagnostic procedure start, see HIGH IMPEDANCE Q Figure 18. Write the status register (after a write enable latch sequence operation A) ...

Page 24

... An activation of this pin puts the bit s0 of the status register to 1 (start diagnostic) like an operation e (diagnostic procedure start). Then an operation F has to be executed without an operation E before. ● After an operation F, the IRQ pin is deactivated, and goes connected to a pull-up resistor. 24/31 L5953 ...

Page 25

... L5953 6 Application note Figure 20. Block and application diagram S1 W1 VOLTAGE WARNING HSD1 HSD1 HSD2 VSPI SPI INTERFACE IRQ Q D Figure 21. Block diagram and application with external power MOS S1 W1 VOLTAGE WARNING HSD1 HSD1 HSD2 VSPI SPI INTERFACE IRQ ...

Page 26

... μ μF C10 = 10 μF C11 = 4 220 kΩ 3.3 kΩ MBR360 STBY ⋅ CTLHy STBY ⎞ ⎟ – ⎠ , .The maximum ripple is o,max ) and the input voltage is sw,min is: min L5953 C6 = 100 kΩ the REG1 ...

Page 27

... L5953 6.3.3 Output capacitor selection The criteria for the selection of the capacitor C7 is based on the output voltage ripple requirements. The ripple on the output voltage is due to a capacitive contribute, often negligible, equal to and a resistive contribute given by the ESR of the capacitor and which is equal to Δ ...

Page 28

... G 0. ESR ⋅ ⋅ = ---------------------- - -------------------------------------------- - R p ⎛ ⎞ ⋅ ------------ - ------- - – 1 ⎝ ⎠ ESR ⋅ = -------------------------- ref PWM ---------------------------------- R2 V ref,PWM – ------------------------ - ⋅ ⋅ ⋅ = ---------------------- - L5953 ...

Page 29

... L5953 7 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 30

... Revision history 8 Revision history Table 13. Document revision history Date 25-Mar-2003 04-Sep-2007 30/31 Revision 1 Initial release. 2 Layout changes and text mofifications. L5953 Changes ...

Page 31

... L5953 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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