ip2021c International Rectifier Corp., ip2021c Datasheet - Page 11

• Manufacturer Part Number: ip2021c
• Description: Synchronous Buck Dual Channel Power Block
• Manufacturer: International Rectifier Corp.

Recommended PCB Layout
PCB Layout Guidelines
The following guidelines are recommended to reduce the parasitic values and optimize overall
performance:
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All pads on the iP2021C footprint design need to be Solder-mask defined (see Figure 11).
Also refer to International Rectifier application notes AN1028 and AN1029 for further footprint
design guidance.
Place as many vias around the Power pads (V
electrical and optimal thermal performance (see Figure 12).
A minimum of three 10µF, X5R, 16V ceramic capacitors per phase of iP2021C are needed for
28A operation at 1MHz. This will result in the lowest loss due to input capacitor ESR.
Placement of the ceramic input capacitors is critical to optimize switching performance. Place
all six ceramic capacitors (C1-C6) right underneath the iP2021C footprint (see Figure 12
Bottom Component Layer).
Dedicate at least two layer for PGND only
Duplicate the Power Nodes on multiple layers (refer to AN1029).
Figure 11 Top Copper and Solder-mask Layer of PCB Layout
8/13/2009
IN1
, V
IN2
, V
SW1
, V
iP2021CPbF
SW2
and PGND) for both
PD-97414
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