mb95f108amwpfv Fujitsu Microelectronics, Inc., mb95f108amwpfv Datasheet - Page 55
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mb95f108amwpfv
Manufacturer Part Number
mb95f108amwpfv
Description
8-bit Proprietary Microcontrollers Cmos 2 F2mc-8fx Mb95100am Series
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
1.MB95F108AMWPFV.pdf
(72 pages)
- Current page: 55 of 72
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Sampling at the falling edge of sampling clock
(ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1)
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the
*2 : Serial clock delay function is used to delay half clock for the output signal of serial clock.
*3 : Refer to “ (2) Source Clock/Machine Clock” for t
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold time
SOT → SCK ↑ delay time
serial clock.
SCK
SOT
SIN
Parameter
2.4 V
0.8 V
Sym-
t
0.8 V
0.2 V
t
t
t
t
SOVHI
bol
SLOVI
SCYC
IVSHI
SHIXI
t
SOVHI
CC
CC
t
IVSHI
SCK, SOT
SCK, SOT
Pin name
SCK, SIN
SCK, SIN
SCK
(Vcc = 5.0 V ± 10%, AVss = Vss = 0.0 V, T
*1
and enabled serial clock delay
MCLK
2.4 V
operating output pin :
C
L
.
= 80 pF + 1 TTL.
Internal clock
Conditions
t
SHIXI
0.8 V
MB95100AM Series
t
SCYC
0.8 V
0.2 V
CC
CC
t
MCLK
t
SLOVI
2.4 V
0.8 V
5 t
Min
− 95
*
MCLK
⎯
3
0
+ 190
*2
*
3
Value
2.4 V
A
= − 40 °C to + 85 °C)
4 t
Max
+ 95
MCLK
⎯
⎯
⎯
*
3
Unit
ns
ns
ns
ns
ns
55
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