mb90f377pff-g Fujitsu Microelectronics, Inc., mb90f377pff-g Datasheet - Page 39

• Manufacturer Part Number: mb90f377pff-g
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: Fujitsu Microelectronics, Inc.

1. Low-power Consumption Control Circuit
Note : Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption.
PERIPHERAL RESOURCES
The MB90370/375 series has the following CPU operating mode selected by the configuration of an operating
clock and clock operation control.
• Clock Mode
• CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral func-
tions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU
while it is accessing a register, internal memory, or peripheral function.
• Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or
the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode) , thereby
reducing power consumption.
• PLL clock mode
• Main clock mode
• Sub-clock mode
• PLL sleep mode
• Main sleep mode
• Sub-sleep mode
• Timebase timer mode
• Watch mode and main watch mode
• Stop mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to operate the CPU
and peripheral functions. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive.
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode. Components
excluding the CPU operate on the divided-by-four sub-clock.
The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer,
and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated.
The watch mode and main watch mode operates the watch timer only. The sub-clock operates but the
main clock and PLL multiplier circuit stop.
The stop mode causes the oscillation to stop. All functions are inactivated.
MB90370/375 Series
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