mb90f378 Fujitsu Microelectronics, Inc., mb90f378 Datasheet - Page 51

• Manufacturer Part Number: mb90f378
• Description: 16-bit Proprietary Microcontroller
• Manufacturer: Fujitsu Microelectronics, Inc.

Notes : • t
*1 : At the stop condition or transferring of next byte.
*2 : After setting register bit IBCRH : SCC at restart.
(7) I
Start condition output
Stop condition output
Start condition detect
Stop condition detect
Restart condition output
Restart condition detect
SCL output “L” width
SCL output “H” width
SDA output delay
SDA output setup time
after interrupt
SCL input “L” pulse
SCL input “H” pulse
SDA output setup time
SDA hold time
2
C / Multi-address I
Parameter
• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4, CS3)” and “MCCR register
• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0)” and “MCCR register
• t
• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.
(CS4, CS3)”. Please refer to the MB90378 series H/W manual for details.
(CS2 to CS0)”. Please refer to the MB90378 series H/W manual for details.
CP
DOSU
is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for t
is shown in the interrupt time is longer than the “L” width of SCL.
2
C Timing
(V
Symbol Pin name
t
t
t
CC
t
t
STASU
STASU
t
t
t
t
t
t
DOSU
HIGH
t
HIGH
t
LOW
LOW
t
STA
STO
STA
STO
DO
HO
SU
= 2.7 V to 3.6 V, AV
SCL,
SCL,
SCL,
SCL,
SCL,
SCL,
SDA
SDA
SDA
SDA
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
t
t
t
t
CP
CP
CP
CP
t
t
CP
CP
CC
(m x n/2 − 1) − 20 t
(m x n/2 + 3) − 20 t
(m x n/2 + 2) − 20 t
(m x n/2 + 3) - 20
x m x n/2 − 20
t
x m x n/2 − 20
t
t
= 2.7 V to 3.6 V, V
CP
CP
CP
t
t
t
t
CP
CP
CP
CP
x 3 − 20
x 4 − 20
x 3 + 40
Min
40
+ 40
+ 40
+ 40
+ 40
0
Value
t
SS
CP
CP
CP
CP
t
CP
= AV
(m x n/2 − 1) + 20
(m x n/2 + 3) + 20
(m x n/2 + 3) + 20
(m x n/2 + 2) + 20
x m x n/2 + 20
t
MB90378 Series
CP
SS
x 3 + 20
Max
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
= 0.0 V, T
A
CP
= −40 °C to +85 °C)
.
Unit Remarks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Master
mode
Master
mode
Master
mode
Master
mode
Master
mode
*1
*2
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