z8f0813 ZiLOG Semiconductor, z8f0813 Datasheet - Page 71
z8f0813
Manufacturer Part Number
z8f0813
Description
High-performance 8-bit Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z8F0813.pdf
(247 pages)
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Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
IRQ1 Enable High and Low Bit Registers
Reserved
R
7
0
Reserved—Must be 0
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Reserved—0 when read
T1ENL—Timer 1 Interrupt Request Enable Low Bit
T0ENL—Timer 0 Interrupt Request Enable Low Bit
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit
ADCENL—ADC Interrupt Request Enable Low Bit
Table 40
registers
Interrupt Request 1 register. Priority is generated by setting bits in each register.
Table 40. IRQ1 Enable and Priority Encoding
where x indicates the register bits from 0–7.
IRQ1ENH[x] IRQ1ENL[x] Priority
0
0
1
1
T1ENL
(Table 41
describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit
R/W
6
0
and
T0ENL
0
1
0
1
R/W
Table
5
0
42) form a priority encoded enabling for interrupts in the
Disabled
Level 1
Level 2
Level 3
U0RENL
R/W
4
0
FC2H
U0TENL
R/W
Description
Disabled
Low
Nominal
High
3
0
Reserved Reserved
Z8 Encore! XP
R
2
0
Product Specification
R
1
0
®
Interrupt Controller
F0823 Series
ADCENL
R/W
0
0
61
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