c8051f912-gdi Silicon Laboratories, c8051f912-gdi Datasheet
c8051f912-gdi
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c8051f912-gdi Summary of contents
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... INTERNAL OSCILLATOR INTERNAL OSCILLATOR External Oscillator HARDWARE smaRTClock HIGH-SPEED CONTROLLER CORE 16 kB 8051 CPU 768 B SRAM ISP FLASH (25 MIPS) FLEXIBLE DEBUG POR INTERRUPTS CIRCUITRY Copyright © 2011 by Silicon Laboratories C8051F912-GDI Compatible SPI o C Port 0 Port 1 Port 2 WDT C8051F912-GDI TM , ...
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... C8051F912-GDI 1. Ordering Information Table 1.1. Product Selection Guide C8051F912-GDI 25 16 768 *Note: 1024 bytes reserved for factory use 2 Rev. 1.0 2 Tested Die in Wafer Form ...
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... Pin Definitions Table 2.1. Pin Definitions for C8051F912-GDI Physical Name Pad Type Number VBAT DC+ P Out DC– GND G GND 3 G DCEN RST I/O C2CK D I/O P2. I/O C2D D I/O XTAL3 XTAL4 9 A Out P0 I ...
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... C8051F912-GDI Table 2.1. Pin Definitions for C8051F912-GDI (Continued) Physical Name Pad Type Number P0 I AGND XTAL1 XTAL2 A Out P0 I Out CNVSTR IREF0 A Out P1 ...
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... Table 2.1. Pin Definitions for C8051F912-GDI (Continued) Physical Name Pad Type Description Number P1 I/O or Port 1. May also be used as NSS for SPI1. P1 I/O or Port 1. P1 I/O or Port 1. P1 I/O or Port 1. C8051F912-GDI Rev. 1.0 5 ...
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... C8051F912-GDI 3. Bonding Instructions Table 3.1. Bond Pad Coordinates Physical Pad Example Number Package Pin Number (QFN-24) 1 Reserved Reserved* 15 Reserved Reserved* 21 Reserved* 22 Reserved* 23 Reserved *Note: Pins marked “Reserved” should not be connected. ...
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... Number (QFN-24 Reserved *Note: Pins marked “Reserved” should not be connected. C8051F912-GDI Package Pin Name Pad Coordinates Relative to Center X (µm) P0.6/CNVSTR 836 P0.5/RX 836 — 745 P0.4/TX 641 P0.3/XTAL2 484 P0.2/XTAL1 342 P0.1/AGND –490 P0.0/VREF –633 Rev. 1.0 Y (µ ...
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... C8051F912-GDI Figure 3.1. Die Bonding (QFN-24) 8 Rev. 1.0 ...
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... Maximum Processing Temperature Electronic Die Map Format Bond Pad Pitch Minimum *Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer). Rev. 1.0 C8051F912-GDI C8051F911B 8 in. 1.9256 mm x 2.0366 mm 12 mil ±1 mil Notch 80 µ ...
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... C8051F912-GDI 4. Wafer Storage Guidelines It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contami- nation. Wafers may be stored for months in the original packaging supplied by Silicon Labs. Wafers must be stored at a temperature of 18–24 °C. Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%. ...
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... N : OTES C8051F912-GDI Rev. 1.0 11 ...
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... C8051F912-GDI C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ...