m30800sagp Renesas Electronics Corporation., m30800sagp Datasheet - Page 14

• Manufacturer Part Number: m30800sagp
• Description: Single-chip 16/32-bit Cmos Microcomputer
• Manufacturer: Renesas Electronics Corporation.

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R
R
2.2 High-Speed Interrupt Registers
2.3 DMAC-Associated Registers
e
E
3
. v
J
2
0
C
Registers associated with the high-speed interrupt are as follows:
Registers associated with DMAC are as follows:
1
3
1 .
8 /
B
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
0
0
2.1.8.5 Register Bank Select Flag (B)
2.1.8.6 Overflow Flag (O)
2.1.8.7 Interrupt Enable Flag (I)
2.1.8.8 Stack Pointer Select Flag (U)
2.1.8.9 Processor Interrupt Priority Level (IPL)
2.1.8.10 Reserved Space
0
0
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0".
The I flag enables a maskable interrupt.
Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is
set to "0" when an interrupt is acknowledged.
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
When writing to a reserved space, set to "0". When reading, its content is indeterminate.
3
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N
8
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u
1
0
p
1
, 1
0
2
0
0
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2. Central Processing Unit (CPU)