r5f3650kcnfb Renesas Electronics Corporation., r5f3650kcnfb Datasheet - Page 74
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r5f3650kcnfb
Manufacturer Part Number
r5f3650kcnfb
Description
M16c/65c Group Renesas Mcu
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F3650KCNFB.pdf
(112 pages)
- Current page: 74 of 112
- Download datasheet (886Kb)
M16C/65C Group
R01DS0015EJ0100 Rev.1.00
Feb 07, 2011
5.2.4
Table 5.36
Notes:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-ALE)
h(BCLK-ALE)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
d(DB-WR)
h(WR-DB)
5.2.4.1
1.
2.
3.
4.
Symbol
(V
CC1
Calculated according to the BCLK frequency as follows:
Calculated according to the BCLK frequency as follows:
This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value.
Hold time of data bus is expressed in
t = − CR × ln(1 − V
by a circuit of the right figure.
For example, when V
low level is
t = − 30 pF × 1 k Ω × In(1 − 0.2V
Calculated according to the BCLK frequency as follows:
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
0.5 10
--------------------- - 40 ns
0.5 10
--------------------- - 10 ns
0.5 10
--------------------- - 20 ns
f
f
= 6.7 ns.
f
(
(
(
BCLK
BCLK
BCLK
×
×
×
= V
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
)
)
)
9
9
9
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
CC2
In No Wait State Setting
Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)
–
–
–
= 5 V, V
[
[
[
]
]
]
OL
f
(BCLK)
/V
SS
OL
CC2
= 0.2V
= 0 V, at T
)
is 12.5 MHz or less.
CC2
CC2
Parameter
, C = 30 pF, R = 1 k Ω , hold time of output
/V
opr
CC2
= -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified)
)
(3)
Figure 5.14
Measuring
Condition
See
(Note 2)
(Note 1)
(Note 4)
Min.
5. Electrical Characteristics
−4
0
0
0
0
0
Standard
V
CC1
DBi
Max.
= V
25
25
15
25
25
40
Page 74 of 109
CC2
= 5 V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
R
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