mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet - Page 25
mb91307r
Manufacturer Part Number
mb91307r
Description
32-bit Microcontroller Cmos Fr60 Mb91307 Series
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
1.MB91307R.pdf
(96 pages)
- Current page: 25 of 96
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2. Internal Architecture
The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction
bus (I-bus) is connected to an on-chip instruction cache. a 32-bit ←→16-bit bus converter is connected to the
bus (F-bus) to provide an interface between the CPU and peripheral resources. The Harvard ←→ Princeton bus
converter is connected to the both the I-bus and D-bus as an interface between the CPU and bus controller.
Instruction
cache
RAM
I address
I data
F address
F data
D-bus
Peripherals resource
R-bus
Bus converter
FRex CPU
32 bit
16 bit
D address
D data
16
I-bus
32
32
32
32
32
32
MB91307 Series
X-bus
Bus controller
Princeton
converter
Harvard
bus
25
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