mb91103 Fujitsu Microelectronics, Inc., mb91103 Datasheet
mb91103
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mb91103 Summary of contents
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... I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91103 normally operates in the external bus access mode and executes instructions on the internal 1 KB cache memory for enhanced performance. ...
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... MB91103 Series (Continued) Bus interface • 24-bit address bus (16 MB memory space) • 32-bit/16-bit/8-bit data bus • Basic external bus cycle: 2 clock cycles • Chip select outputs for setting down to a minimum memory block size bytes: 6 • Interface supported for various memory technologies ...
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... Low power consumption mode Sleep mode/stop mode • Clock gear function Operating clocks for CPU and peripherals are independently selective Gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) • Package QFP-160 • CMOS technology (0.65 m), operating voltage 5.0 V 10% To Top / Lineup / Index MB91103 Series 3 ...
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... MB91103 Series PRODUCT LINEUP Product Items Instruction cache 1 KB fixed DMAC 5 channels (ch. 0, ch. 1, ch. 4, ch. 5 and ch. 6 only) Address register (32-bit length) (DMAAR 0, DMAAR 1) Address register (16-bit length) (DMAAR 2 to DMAAR 7) Transfer count register (16-bit length) (DMACT 0, DMACT 1) Transfer count register (8-bit length) (DMACT 4 to DMACT 6) Channels for cycle steal operation: 2 channels (ch ...
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... D25 30 D26 31 D27 D28 34 D29 35 D30 36 D31 37 A00 38 A01 39 A02 40 Note: No connections to N.C. pins. MB91103 Series (Top view) (FPT-160P-M03) To Top / Lineup / Index SO0/PE5 120 119 SI0/PE4 118 INT3/PE3 INT2/PE2 117 116 INT1/PE1 115 INT0/PE0 V 114 SS 113 AN7/PD7 112 AN6/PD6 111 ...
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... MB91103 Series PIN DESCRIPTION Pin No. Pin name QFP* 158 X0 159 MD0 to MD2 156 RST D00 to D07 P00 to P07 10 to 13, D08 to D15 P10 to P17 20 to 23, D16 to D23 P20 to P27 29 to 32, D24 to D31 45, A00 to A15 ...
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... Can be configured as I/O port. C CASH output for DRAM bank 0. Can be configured as I/O port. C CASL output for DRAM bank 1. Can be configured as I/O port. To Top / Lineup / Index MB91103 Series Function 16-bit bus width 8-bit bus width WR0 WR0 WR1 (I/O port enabled) (I/O port enabled) ...
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... MB91103 Series Pin No. Pin name QFP* 94 CS1H PB5 95 DW0 PB6 96 DW1 PB7 100 HST 101 NMI 102 to 105 AN0 to AN3 PD0 to PD3 110 to 113 AN4 to AN7 PD4 to PD7 115 to 118 INT0 to INT3 PE0 to PE3 119 SI0 PE4 120 SO0 PE5 121 ...
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... General-purpose I/O ports. E I/O ports of open-drain type. C Transfer request acknowledge output pin for DMAC (ch. 0). This function is available when transfer request output for DMAC is enabled. General-purpose I/O port. This function is available when transfer request for DMAC is disabled. To Top / Lineup / Index MB91103 Series Function (Continued) 9 ...
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... MB91103 Series Pin No. Pin name QFP* 135 DACK1 INT6 ATG PG1 136 DREQ0 PG2 137 DREQ1 INT7 PG3 138 TI0 PG4 139 TO0 PG5 * : FPT-160P-M03 10 Circuit type I External transfer request acknowledge output pin for DMAC (ch. 1). This function is available when transfer request output for DMAC is enabled ...
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... This pin is used for input when input to the counter is enabled in phase-shift count mode or up/down count mode, and it is necessary to disable output for other functions from this pin unless such output is made intentionally. General-purpose I/O port. To Top / Lineup / Index MB91103 Series Function (Continued) 11 ...
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... MB91103 Series Pin No. Pin name QFP* 145 IC2 BIN1 PH2 146 IC3 ZIN1 PH3 147 OC0 PH4 148 OC1 PH5 149 OC2 PH6 151 OC3 PH7 * : FPT-160P-M03 12 Circuit type F Input pin for input capture 2 (ICU2). This pin is used for input when ICU is in edge detect operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally ...
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... Reference voltage input (High) for A/D converter. Make sure to turn on and off this pin with potential of AVRH or more applied — Reference voltage input pin (Low) for A/D converter. — Power supply pin (V ) for A/D converter Top / Lineup / Index MB91103 Series Function 13 ...
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... MB91103 Series DRAM CONTROL PIN Data bus 32-bit mode Pin name 2CAS/1WE mode 1CAS/2WE mode 2CAS/1WE mode 1CAS/2WE mode RAS0 Area 4 RAS RAS1 Area 5 RAS CS0L CAS0 * 1 CS0H 1 CAS1 * CS1L CAS2 * 1 CS1H CAS3 * 1 DW0 WE DW1 WE * and 3 respectively corresponds to the lowest 2 bits of address as follows: 0: “ ...
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... SS C P-ch N-ch R Standby control signal D P-ch N-ch R Standby control signal MB91103 Series • Oscillation feedback resistance 1 M approx. With Standby control Clock input • CMOS level hysteresis input Without standby control With pull-up resistance Digital input • CMOS level I/O With standby control Digital output ...
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... MB91103 Series Type E R Standby control signal F R Standby control signal Circuit • N-ch open-drain output • CMOS level output P-ch N-ch Digital output Digital input • CMOS level output • CMOS level hysteresis input P-ch N-ch Digital output Digital input • CMOS level I/O ...
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... CMOS level output • TTL level input P-ch Digital output N-ch Digital output Digital input TTL • CMOS level input/output • Large current drive P-ch Digital output N-ch Digital output Digital input To Top / Lineup / Index MB91103 Series Remarks Without standby control With standby control With standby control 17 ...
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... MB91103 Series HANDLING DEVICES 1. Preventing Latchup In CMOS ICs, applying voltage higher than V rating across V and V may cause latchup This phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. Make sure to prevent the voltage from exceeding the maximum rating. ...
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... External Reset Input Keep the RST pin level at “L” for at least 5 machine cycles to ensure proper reset operation. 11. I/O Access Limmitations When Using Gear Function In MB91103 series, there are some limmitations concerning about accesses to the I/O area. Limitted I/O area: 0X10 to 0XFF H ...
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... As interrupting controllers ICR00 and ICR01 are put in this address, there is no bad influence owing to dummy read-out operations. 12. DMAC Limitations When Using Gear Function In MB91103 series, UART operated in synclonizing transfer mode must not be DMA transfer facter. Clock gear combinations: Peripheral ...
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... PG0 to PG7 8 PH0 to PH7 4 PI0 to PI3 Other pins MD0 to MD2 CC SS MB91103 Series FR20 CPU Instruction cache Bus converter (Harvard Princeton) Bus controller DRAM controller Port 0 to port B UART (2 ch.) U-TIMER (2 ch.) (Baud rate timer) Extended I/O serial interface Real-time I/O time ...
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... CPU CORE 1. Memory Space The FR20 series has a logical address space bytes (2 space. The MB91103 has no internal memories (RAM, ROM). • Memory space • Direct addressing area The following areas on the memory space are assigned to direct addressing area for I/O. In these areas, an address can be specifi ...
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... System stack pointer User’s stack pointer Multiplication/division result register ILM0 — — SCR To Top / Lineup / Index MB91103 Series Initial value XXXX XXXX not fixed H 000F FC00 H XXXX XXXX not fixed H 0000 0000 H XXXX XXXX not fixed H ...
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... MB91103 Series • Condition code register (CCR) S flag : Specifies a stack pointer used as R15. I flag : Controls user interrupt request enable/disable. N flag : Indicates sign bit when division result is assumed the 2’s complement format. Z flag : Indicates whether or not the result of division was “0”. ...
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... Of the above 16 registers, following registers have special functions. To support the special functions, part of the instruction set has been sophisticated to have enhanced functions. R13: Virtual accumulator (AC) R14: Frame pointer (FP) R15: Stack pointer (SP) Upon reset, values R14 are not fixed. Value in R15 is initialized to be 00000000 MB91103 Series 32 bits Initial value XXXX XXXX : : ...
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... External vector mode Internal vector mode 1 — — — MB91103 does not support single-chip mode. 2. Registers • Mode setting registers and modes Address 0000 07FF Write only X : Not fixed : Always write “0” except for M1 and M0. • Bus mode setting bits and functions ...
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... SSR1 Serial status register 1 H 0021 SIDR1/SODR1 Serial input register 1/Serial output register 1 H 0022 SCR1 Serial control register 1 H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value ...
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... MB91103 Series Register name Address (Abbreviated) 0023 SMR1 H 0024 H to 0027 H 0028 H TMRLR0 0029 H 002A H TMR0 002B H 002C H 002D H 002E H TMCSR0 002F H 0030 H TMRLR1 0031 H 0032 H TMR1 0033 H 0034 H 0035 H 0036 H TMCSR1 0037 H 0038 H ADCR 0039 H 003A H ADCS 003B H 003C H to ...
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... H 0068 H OPCP4 Output compare register ch. 4 0069 H 006A H OPCP5 Output compare register ch. 5 006B H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value R ...
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... MB91103 Series Register name Address (Abbreviated) 006C H OCS3 006D H 006E H 006F H 0070 H OPCP6 0071 H 0072 H OPCP7 0073 H 0074 H TCDT 0075 H 0076 H 0077 TCCS H 0078 H UTIM0/UTIMR0 0079 H 007A H 007B UTIMC0 H 007C H UTIM1/UTIMR1 007D H 007E H 007F UTIMC1 H 0080 H to 0083 H 0084 H UDCR0 0085 ...
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... H 0203 H 0204 H 0205 H DMAC-ch. 0 DMACC0 addressing/count setting register 0206 H 0207 H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value – R/W – R/W ...
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... MB91103 Series Register name Address (Abbreviated) 0208 H 0209 H DMACS1 020A H 020B H 020C H 020D H DMACC1 020E H 020F H 0210 H to 021F H 0220 H 0221 H DMACS4 0222 H 0223 H 0224 H 0225 H DMACC4 0226 H 0227 H 0228 H 0229 H DMACS5 022A H 022B H 022C H 022D H DMACC5 022E H 022F H 0230 H 0231 ...
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... H 0253 H 0254 H 0255 H DMAAR5 DMAC address register 5 0256 H 0257 H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value – R ...
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... MB91103 Series Register name Address (Abbreviated) 0258 H 0259 H DMAAR6 025A H 025B H 025C H 025D H DMAAR7 025E H 025F H 0260 H DMACT0 0261 H 0262 H DMACT1 0263 H 0264 H to 0267 H 0268 H DMACT4 0269 H 026A H DMACT5 026B H 026C H DMACT6 026D H 026E H to 0273 H 0274 H 0275 H DMACR 0276 ...
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... ICR11 Interrupt control register 11 H 040C ICR12 Interrupt control register 12 H 040D ICR13 Interrupt control register 13 H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value ...
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... MB91103 Series Register name Address (Abbreviated) 040E ICR14 H 040F ICR15 H 0410 ICR16 H 0411 ICR17 H 0412 ICR18 H 0413 ICR19 H 0414 ICR20 H 0415 ICR21 H 0416 ICR22 H 0417 ICR23 H 0418 ICR24 H 0419 ICR25 H 041A ICR26 H 041B ICR27 H 041C ICR28 H 041D ICR29 H 041E ICR30 H 041F ...
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... H AMR1 Area mask register 1 060F H 0610 H ASR2 Area select register 2 0611 H MB91103 Series Register name Read/write To Top / Lineup / Index Initial value R/W – – – R/W – – – R/W – – – – – – – 0 ...
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... MB91103 Series Register name Address (Abbreviated) 0612 H AMR2 0613 H 0614 H ASR3 0615 H 0616 H AMR3 0617 H 0618 H ASR4 0619 H 061A H AMR4 061B H 061C H ASR5 061D H 061E H AMR5 061F H 0620 AMD0 H 0621 AMD1 H 0622 AMD32 H 0623 AMD4 H 0624 AMD5 H 0625 DSCR H 0626 H RFCR ...
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... ICR05 00000405 22 16 ICR06 00000406 23 17 ICR07 00000407 24 18 ICR08 00000408 To Top / Lineup / Index MB91103 Series Read/write Initial value W – – – – – Interrupt vector * Vector Offset address address — 3FC 000FFFFC H — ...
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... MB91103 Series Interrupt causes External interrupt 7 Reserved for system UART0 receive complete UART1 receive complete Reserved for system UART0 transmit complete UART1 transmit complete Reserved for system DMAC0 (complete, error) DMAC1 (complete, error) Reserved for system Reserved for system DMAC4 (complete, error) ...
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... ICR45 0000042D 62 3E ICR46 0000042E 63 3F ICR47 0000042F 64 40 — — — 255 FF To Top / Lineup / Index MB91103 Series 1 Interrupt vector * Vector Offset address address 31C 000FFF1C H H 318 000FFF18 H H 314 000FFF14 H H 310 000FFF10 H H 30C ...
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... MB91103 Series PERIPHERAL RESOURCES 1. I/O Ports There are 2 types of I/O port register structure — port data register (PDR0 to PDRI) and data direction register (DDR0 to DDRI, AIC), where bits PDR0 to PDR I and bits DDR0 to DDRI corresponds respectively. Each bit on the register corresponds to an external pin. In port registers input/output register of the port configures input/ output function of the port, while corresponding bit (pin) confi ...
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... B H XXXXXXXX (R/W) 0000D3 B H XXXXXXXX (R/W) 0000D4 B H XXXXXXXX (R/W) 0000D5 XXXX (R/W) 0000D6 B H 0000D7 H To Top / Lineup / Index MB91103 Series Initial value bit 0 DDR0 00000000 (W) B DDR1 00000000 (W) B DDR2 00000000 (W) B DDR6 00000000 (W) B DDR8 000- - 000 (W) B DDR9 - - 000000 ...
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... MB91103 Series 2. DMA Controller (DMAC) The DMA controller is a module embedded series devices, and performs DMA (Direct Memory Access) transfer. DMA transfer performed by the DMA controller transfers data without intervention of CPU, contributing to enhanced performance of the system. • Block diagram External transfer ...
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... DMACS5 DMACC5 DMACS6 DMACC6 DMAAR0 DMAAR1 DMAAR2 * 1 DMAAR3 * 1 DMAAR4 * 1 DMAAR5 * 1 1 DMAAR6 * DMAAR7 * 1 DMACT0 DMACT1 DMACT4 * 2 3 DMACT5 * DMACT6 * 2 DMACR * 1 bit 16 XXX B B Fixed bit 8 bit 0 B Fixed bit 8 bit 0 00000000 B Fixed To Top / Lineup / Index MB91103 Series Access bit 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W bit 0 45 ...
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... MB91103 Series 3. UART The UART is a serial I/O port for supporting asynchronous (start-stop system) communication or CLK synchronous communication. The MB91103 consists of 2 channels of UART. • Block diagram Control signals From U-TIMER Clock select circuit From external clock SCI SI (Receive data) Receive status ...
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... It can be selected from 10/20/80/160/320 frequency division of machine clock. External shift clock mode : In this mode, data transfer operation is synchronized with clock input from external pin (SC0). Data transfer by CPU instructions is enabled when the general port sharing the external pin (SC0 configured. MB91103 Series bit 8 bit 0 SCR0 ...
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... MB91103 Series • Block diagram (MSB first SI0 SDR (serial data register) SO0 SC0 Internal clock 2 1 SMD2 SMD1 SMD0 SMCS • Registers Address 0000001A H 00000019 H Access type(s) in parenthesis R/W : Read and write access type – : Vacant X : Not fixed 48 R – BUS ...
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... The U-TIMER is a 16-bit timer for generating UART baud rate. Combination of chip operating frequency and reload value of U-TIMER allows flexible setting of baud rate. The U-TIMER operates as an interval timer by using interrupt issued on counter underflow. The MB91103 has 2 channel U-TIMER embedded on the chip. By combining 2 interval timers in cascade, an interval can be counted. • ...
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... The input pin (TI) is configured as an event input in the event count mode, a trigger input in the internal clock mode and also operates as a gate input. The external event count function in the reload mode can operate as a external clock divider. The MB91103 consists of 2 channels of 16-bit reload timer. • Block diagram 16 ...
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... The 16-bit input/output timer consists of a 16-bit free-run timer, 8 output compares and 4 input capture modules. By using these functions, 8 independent wave outputs based on the 16-bit free-run timer as well as input pulse width measurement and external clock cycle measurement can be realized. MB91103 Series Initial value bit 0 ...
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... MB91103 Series • Block diagram 16-bit free-run timer Output compare 0 Output compare 1 Output compare 2 Output compare 3 Input capture 0 Input capture 1 52 Control logic 16-bit timer Clear Compare register 0 Compare register 1 Compare register 2 Compare register 3 Compare register 4 Compare register 5 Compare register 6 Compare register 7 ...
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... H Access type(s) in parenthesis R/W : Read and write access type Interrupt request STOP MODE CLR CLK1 CLK0 Comparator 0 16-bit up counter bit 8 bit 0 TCDT TCCS To Top / Lineup / Index MB91103 Series Divider Clock T15 to T00 Count value output Initial value 00000000 B (R/W) 00000000 B 00000000 (R/ ...
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... MB91103 Series (2) Output Compare The output compare consists of a 16-bit compare register, compare output pin block and a control register. When the value set in the compare register matches with the 16-bit free-run timer value, output level is reversed, enabling an interrupt request to be issued. ...
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... H 0000006C H Access type(s) in parenthesis R/W : Read and write access type – : Vacant X : Not fixed MB91103 Series Initial value bit OPCP0 OPCP1 OPCP2 ...
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... MB91103 Series (3) Input Capture The input capture consists of input capture data registers and input capture control status registers. The input capture detects a rising edge, a falling edge or both edges of external input signal and hold the 16-bit free-run timer value at the moment into the register. The input capture can issue an interrupt upon edge detection, if enabled ...
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... Up/down Counter The up/down counter consists of 3 event input pins, a 16-bit up/down counter, 16-bit reload/compare register and peripheral circuits (control/status register) controlling these functions. The MB91103 consists of 2 channels of counter/timer. • Block diagram CCR CGE1 CGE0 CGSC ZIN Edge/level detect UDCC ...
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... MB91103 Series • Registers Address 00000084 H 0000008C H 00000086 H 0000008E H 0000008B H 00000093 H 00000088 H 00000090 H Access type(s) in parenthesis R/W : Read and write access type R : Read only W : Write only – : Vacant 58 bit 15 bit 8 UDCR0 UDCR1 RCR0 RCR1 CSR0 CSR1 CCR0 CCR1 To Top / Lineup / Index Initial value ...
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... H 000003F4 H 000003F8 H 000003FC H Access type(s) in parenthesis R/W : Read and write access type R : Read only W : Write only MB91103 Series Input latch Detection mode Single-detection data recovery Bit search circuit Search result Initial value bit 16 bit 0 XXXXXXXX XXXXXXXX BSD0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ...
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... MB91103 Series 10. A/D Converter The A/D converter converts an analog input voltage to a digital value. • Block diagram MPX AN0 AN1 AN2 AN3 Analog AN4 input AN5 AN6 AN7 Trigger start ATG TIM0 (internal connection) (Reload timer ch.0) (Peripheral clock) • Registers Address bit 15 0000003A ...
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... LEVEL5 to LEVEL0 are interrupt level outputs. *5: VCT5 to VCT0 are interrupt vector outputs. IM Priority judgment 5 NMI processing 4 Level judgment Level vector generation ICR00 6 Vector judgment ICR47 R – BUS To Top / Lineup / Index MB91103 Series LEVEL4 to LEVEL0* 4 HLDREQ cancel HLDCAN* 3 request VCT5 to VCT0 ...
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... MB91103 Series • Registers Address bit 7 00000400 ICR00 H 00000401 ICR01 H 00000402 ICR02 H 00000403 ICR03 H 00000404 ICR04 H 00000405 ICR05 H 00000406 ICR06 H 00000407 ICR07 H 00000408 ICR08 H 00000409 ICR09 H 0000040A ICR10 H 0000040B ICR11 H 0000040C ICR12 H 0000040D ICR13 H 0000040E ICR14 H 0000040F ICR15 H 00000410 ICR16 H ICR17 ...
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... Access type(s) in parenthesis R/W : Read and write access type Interrupt enable register (ENIR) Cause F/F Edge detection circuit Interrupt cause register (EIIR) Request level setting register (ELVR) bit 8 ENIR EIRR ELVR To Top / Lineup / Index MB91103 Series 9 INT0 to INT7 NMI Initial value bit 0 00000000 (R/W) B (R/W) 00000000 ...
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... MB91103 Series 13. Clock Generation/control Block The clock generation/control block consists of the following 6 blocks: • CPU clock generation (including gear function) • Peripheral clock generation (including gear function) • Reset generation and cause hold • Standby function • DMA request prohibit • PLL (duty ratio adjustment circuit included) • ...
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... Access type(s) in parenthesis R/W : Read and write access type – : Not used bit 8 bit 0 STCR PDRR CTBR GCR WPR DMCR4 DMCR5 To Top / Lineup / Index MB91103 Series Initial value (R/ (R/W) B (R/ (W) B ...
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... MB91103 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage Analog supply voltage * 1 Analog reference voltage * 1 Analog reference voltage * 1 Input voltage * 2 Output voltage * 2 “L” level maximum output current * “L” level average output current * “L” level maximum total output current “ ...
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... Analog supply voltage AV CC AVRH Analog reference voltage AVRL Operating temperature T A Value Unit Min. Max. 4.5 5.5 V 3.0 5 – AVRL AVRH V SS –10 + Top / Lineup / Index MB91103 Series ( Remarks Normal operation Retaining the RAM state in stop mode 67 ...
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... MB91103 Series V (V) CC 5.5 4.5 0 0.625 Internal clock CPP (MHz) 25 1.25 0.625 0 Note: Use external clock if source oscillating clock > 25 MHz. PLL oscillation stabilizing period > 100 s WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device’s electrical characteristics are warranted when operated within these ranges. ...
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... 0. MHz C — 5 MHz C — 5 — — Top / Lineup / Index MB91103 Series = 0 – + Value Unit Remarks Typ. Max. — 0 Hysteresis — 0 input — 0.3 V TTL level CC – ...
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... MB91103 Series 4. AC Characteristics (1) Clock Timing Rating Parameter Clock frequency Clock cycle time Frequency shift ratio (when locked) * Input clock pulse width Input clock rising/falling time Internal operating clock frequency Internal operating clock cycle time *1: Frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system ...
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... Max CYC CLK (V = +5 Condition CLK 1/2 CLK — 1/2 CLK CYC t t CLCH CHCL 2 Top / Lineup / Index MB91103 Series = 0 – + Value Unit Remarks Min. Max. t — 1/2 t CYC CYC – ...
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... MB91103 Series The relation between X0 input and clock output for configured by CHC/CCK1/CCK0 settings of GCR (Gear control register follows: X0 input (1) Source oscillation x 1 (CHC bit of GCR set to “0”) (a) Gear x 1 clock output CCK1/0: “00” (b) Gear x 1/2 x clock output CCK1/0: “ ...
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... No damping resistance required and C internally connected Recommended circuit (3 contacts (158) Circuit parameter Model C1 [pF] 30 (30) 15 (15 (5) To Top / Lineup / Index MB91103 Series X1 (159 internally connected Murata Mfg. Co., Ltd. Contact type [pF] ...
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... MB91103 Series • SMD type Frequency range [MHz] CSACS 10.00 to 13.00 CSTCS CSACS 13.01 to 15.99 CSTCS CSACS 16.00 to 19.99 CSTCS CSACS 20.00 to 25.00 CSTCS *1: Feed-back resistance Rf internally connected in LSI. *2: No damping resistance required and C internally connected (3) Reset Input Symbol Pin name Condition Parameter Reset input time t RST 74 Model ...
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... OSC Set RST pin to "L" level when turning on the device, at least t t supply voltage reaches Vcc is necessary RSTL before turning the RST to "H" level. To Top / Lineup / Index MB91103 Series = 0 – + Unit Remarks Max. V < 0.2 V ...
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... MB91103 Series (5) Normal Bus Access Read/write Operation Symbol Parameter t CS0 to CS5 delay time t Address delay time t Data (parity) delay time delay time t t WR0 to WR3 delay time t Valid address valid data t (parity) input time RD valid data (parity) t input time Data (parity) set up ...
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... A23 to A00 0 D31 to D00 PAR0 to PAR3 WR0 to WR3 t CHDV D31 to D00 2.4 V PAR0 to PAR3 0.8 V BA2 CYC 2.4 V 0 CLRL 2 RLDV t AVDV 2.4 V Read 0 CLWL 2.4 V 0.8 V Write To Top / Lineup / Index MB91103 Series 2 CHCSH 2.4 V 2 CLRH t RHDX 2 DSRH t CLWH 2 ...
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... MB91103 Series (6) Time-sharing Bus Read/Write Operation Symbol Parameter t ALE delay time t t CS1 delay time t Address delay time t Data delay time delay time t t WR0, WR1 delay time t RD valid data input time t Data set up RD time t RD data hold time ...
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... CHAV WR0, WR1 2.4 V A23 to A00 0.8 V (non-multiplexed t bus) CHAV MA2 BA1 2.4 V 2.4 V 0 CLLL CLLH 0.8 V 2.4 V Address 0.8 V Address t CHDV To Top / Lineup / Index MB91103 Series BA2 2 CHCSH 2 DSRH t RLDV 2.4 V 2.4 V Read 0 RHDX 2 CLRH t CLRL 2.4 V 2.4 V Write 0 ...
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... MB91103 Series (7) Ready Input Timing Symbol Pin name Condition Parameter t ACLK delay time t RDY set up time ACLK t ACLK RDY hold time t 2.4 V CLK ACLK RDY When wait(s) is inserted. RDY When no wait is inserted +5 CLAKH CLK ACLK CLAKL RDY — ...
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... V 10 Min. — CLK BGRNT — — t – 10 CYC BGRNT t – 10 CYC t CYC 2 CHBGL 0 XHAL High impedance To Top / Lineup / Index MB91103 Series = 0 – + Value Unit Remarks Max CYC CYC 2 CHBGH 2 HAHV 2 ...
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... MB91103 Series (9) Normal DRAM Mode Read/Write Cycle Symbol Parameter t CLRAH RAS delay time t CHRAL t CLCASL CAS delay time t CLCASH ROW address delay time t CHRAV COLUMN address delay t CHCAV time t CHDWL DW delay time t CHDWH Output data (parity) delay t CHDV1 time RAS valid data (parity) ...
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... D31 to D00 2.4 V 0.8 V PAR0 to PAR3 t CHDV1 2.4 V 0 CHRAL t CHCAV t CHRAV 2.4 V 2.4 V 2.4 V ROW address 0.8 V 0 RLDV 0 CHDWL Write To Top / Lineup / Index MB91103 Series Q5 2 CLCASH t CLCASH 2.4 V 0.8 V 2.4 V COLUMN address 0 CLDV CADH 2.4 V 2.4 V Read 0.8 V 0 CHDWH 2 ...
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... MB91103 Series (10) Normal DRAM Mode Fast Page Read/Write Cycle Symbol Parameter RAS delay time t CLRAH t CLCASL CAS delay time t CLCASH COLUMN address delay t CHCAV time DW delay time t CHDWH Output data (parity) delay t CHDV1 time CAS valid data (parity) t CLDV input time ...
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... PAR0 to PAR3 0 CLCASL t CLCASH 2 CHCAV 2.4 V 2.4 V COLUMN address 0 CLDV CADH 2.4 V 2.4 V Read 0 CHDV1 2.4 V 2.4 V 2.4 V Write 0.8 V 0 Top / Lineup / Index MB91103 Series Q5 2 CLRAH 2.4 V 2.4 V COLUMN address 0.8 V 2.4 V 2.4 V Read 0 CHDWH 2.4 V 2.4 V Write 0 ...
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... MB91103 Series (11) CBR Refresh Symbol Pin name Condition Parameter t RAS delay time t t CAS delay time t CAS: CS0L to CS1H pins are for CAS signal outputs. CLK RAS CAS +5 CLRAH CLK RAS CHRAL — CLCASL CLK CAS CLCASH t CYC ...
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... V 10 Min. — CLK RAS — — — CLK CAS — SR2 SR3 2 CHRAL 0 CLCASL To Top / Lineup / Index MB91103 Series = 0 – + Value Unit Remarks Max SR3 0 CLRAH 2 ...
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... MB91103 Series (13) UART Timing Symbol Pin name Condition Parameter Serial clock cycle time t SCLK SOUT delay time t Valid SIN SCLK t SCLK valid SIN hold t time Serial clock “H” pulse width t Serial clock “L” pulse width t SCLK SOUT delay time t ...
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... CYCP t SCYC 2 SLOV 2 IVSH 2 SLSH 2 SLOV 2 IVSH 2 Top / Lineup / Index MB91103 Series = 0 – + Value Unit Remarks Max. — — ns — ns — ns — ns Max. external CYCP frequency is 2 MHz — ...
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... MB91103 Series (15) Timer System Input Timing Symbol Pin name Condition Parameter t Input pulse width t Note cycle time of peripheral system clock. CYCP TI0, TI1 (16) Trigger System Input Timing Symbol Pin name Condition Parameter A/D start trigger input time t Input capture input trigger ...
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... BIN0 4 t CYCP BIN1 — CYCP 4 t CYCP 4 t CYCP 4 t CYCP 4 t CYCP 4 t CYCP ZIN0 ZIN1 4 t CYCP To Top / Lineup / Index MB91103 Series = 0 – + Unit Remarks Max. — ns — ns — ns — ns — ns — ns — ns — ...
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... MB91103 Series 2.4 V AIN BIN 2.4 V BIN AIN 2.4 V ZIN 92 t AHL 2 AUBU BUAD ADBD 2 BHL t BHL 2 BUAU AUBD BDAD 2 AHL 2 ZHL 0 Top / Lineup / Index t ALL 2 BDAU 0 BLL t BLL 2 ADBU 0 ALL t ZLL ...
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... Value Min. DREQ0 2 t CYC DREQ1 DACK0 — t CYC DACK1 DACK0 t CYC DACK1 2 DRWH 2 DAWH 2 DAWL 0 Top / Lineup / Index MB91103 Series = 0 – + Unit Remarks Max. — CYC CYC 2.4 V 2 ...
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... MB91103 Series 5. A/D Conversion Block Electrical Characteristics ( +4 +5 Parameter Resolution Total error Linearity error Differentiation linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current ...
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... Actual conversion characteristic Ideal characteristic 0.5 LSB' Analog input V Total error of = [V] digital output voltage for causing transition of digital output from (N– Top / Lineup / Index MB91103 Series “11 1111 1111”). NT AVRH – {1 LSB' (N – 0.5 LSB LSB' (Continued) 95 ...
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... MB91103 Series (Continued) Linearity error 3FF Actual conversion characteristic 3FE {1 LSB (N – 3FD 004 003 002 Ideal characteristic 001 V (measured value) OT AVRL Analog input V – {1 LSB' Linearity error NT of digital output – V FST OT 1 LSB = [V] 1022 voltage for causing transition of digital output from (000) ...
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... OUTPUT VS LOAD CAPACITANCE CHARACTERISTIC t (ns) 3.5 3 2.5 2 1 Output vs load capacitance characteristic 95 100 105 To Top / Lineup / Index MB91103 Series 120 C (pF) 110 115 97 ...
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... MB91103 Series INSTRUCTIONS 1. How to Read Instruction Set Summary Mnemonic ADD Rj ADD #s5 (1) (2) (1) Names of instructions. Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels. (2) Addressing modes specified as operands are listed in symbols. ...
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... Register relative indirect (disp8: –0X80 to 0X7F) @(R15, udisp6) : Register relative (udisp6 60, multiple of 4 only) @Ri+ : Register indirect with post-increment (R0 to R15, AC, FP, SP) @R13+ : Register indirect with post-increment (R13, AC) @SP+ : Stack pop @–SP : Stack push (reglist) : Register list To Top / Lineup / Index MB91103 Series 99 ...
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... MB91103 Series 3. Instruction Types Type A Type B Type C Type *C’ Type D Type E Type F 100 MSB 16 bit i8/ u4/ ADD, ADDN, CMP, LSL, LSR and ASR instructions only OP s5/ u8/rel8/dir/reglist 8 OP SUB- rel11 Top / Lineup / Index LSB ...
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... C C – – 1+ – – (Ri 1+ – – (Ri 1+ – – (Ri Top / Lineup / Index MB91103 Series Remarks MSB is interpreted as a sign in assembly language Ri Zero-extension Ri Sign-extension Ri Add operation with sign MSB is interpreted as a sign in assembly language Ri Zero-extension ...
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... MB91103 Series • Bit manipulation instructions Mnemonic BANDL #u4, @Ri BANDH #u4, @Ri * BAND #u8, @Ri * BORL #u4, @Ri BORH #u4, @Ri * BOR #u8, @Ri * BEORL #u4, @Ri BEORH #u4, @Ri * BEOR #u8, @Ri * BTSTL #u4, @Ri BTSTH #u4, @Ri *1: Assembler generates BANDL if result of logical operation “u8&0x0F” leaves an active (set) bit and generates BANDH if “ ...
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... – – – – (R13 + Rj – – – – (R14 + disp8) o8, disp10, disp9, disp8 are signed To Top / Lineup / Index MB91103 Series Remarks Ri Logical shift Logical shift Logical shift Ri Ri ...
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... MB91103 Series • Memory store instructions Mnemonic ST Ri, @Rj ST Ri, @(R13, Rj) ST Ri, @(R14, disp10) ST Ri, @(R15, udisp6) ST Ri, @–R15 ST Rs, @–R15 ST PS, @–R15 STH Ri, @Rj STH Ri, @(R13, Rj) STH Ri, @(R14, disp9) STB Ri, @Rj STB Ri, @(R13, Rj) STB Ri, @(R14, disp8 Assembler calculates and set the result in the field of o8, o4 format given by hardware specification. ...
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... PCs/(V xor 2/1 – – – – PCs 2/1 – – – – PCs rel8, label12, label9 are signed. To Top / Lineup / Index MB91103 Series Remarks PC RP Return (SSP), I flag (SSP), For emulator S fl ...
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... MB91103 Series • Branch instructions with delays Mnemonic JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9 BC:D label9 BNC:D label9 BN:D label9 BP:D label9 BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9 BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9 Notes: • ...
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... R15 – u10 9F–9 b – – – – R14 + 4 (R15 – – – – – Rj TEMP (Rj) Ri TEMP To Top / Lineup / Index MB91103 Series Remarks CCR CCR Set ILM immediate value ADD SP instruction 32-bit 32-bit 32 bit 32-bit Load-multi Load-multi R8 to R15 ...
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... MB91103 Series • 20-bit normal branch macro instructions Mnemonic * CALL20 label20 BRA20 label20 BEQ20 label20 BNE20 label20 BC20 label20 BNC20 label20 BN20 label20 BP20 label20 BV20 label20 BNV20 label20 BLT20 label20 BGE20 label20 BLE20 label20 BGT20 label20 BLS20 label20 BHI20 label20, Ri *1: CALL20 (1) If label20– ...
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... If label20–PC–2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:20 #label20, Ri JMP:D @Ri false: MB91103 Series Operation RP, label20 Top / Lineup / Index Remarks PC 1 Ri: Temporary register * Ri: Temporary register * ...
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... MB91103 Series • 32-bit normal macro branch instructions Mnemonic * CALL32 label32 BRA32 label32 BEQ32 label32 BNE32 label32 BC32 label32 BNC32 label32 BN32 label32 BP32 label32 BV32 label32 BNV32 label32 BLT32 label32 BGE32 label32 BLE32 label32 BGT32 label32 BLS32 label32 BHI32 label32, Ri *1: CALL32 (1) If label32– ...
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... If label32–PC–2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; Bxcc false xcc is a revolt condition of cc LDI:32 #label32, Ri JMP:D @Ri false: MB91103 Series Operation RP, label32 Top / Lineup / Index Remarks PC 1 Ri: Temporary register * Ri: Temporary register * ...
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... MB91103 Series • Direct addressing instructions Mnemonic DMOV @dir10, R13 DMOV R13, @dir10 DMOV @dir10, @R13+ DMOV @R13+, @dir10 DMOV @dir10, @–R15 DMOV @R15+, @dir10 DMOVH @dir9, R13 DMOVH R13, @dir9 DMOVH @dir9, @R13+ DMOVH @R13+, @dir9 DMOVB @dir8, R13 DMOVB ...
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... ORDERING INFORMATION Part number MB91103 Package 160-pin Plastic QFP FPT-160P-M03 To Top / Lineup / Index MB91103 Series Remarks 113 ...
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... MB91103 Series PACKAGE DIMENSIONS 160-pin Plastic QFP (FPT-160P-M03) 32.00±0.40(1.260±.016)SQ 28.00±0.20(1.102±.008)SQ 120 121 INDEX 160 LEAD No. 1 0.65(.0256)TYP 1994 FUJITSU LIMITED F160004S-3C-2 C 114 3.85(.152)MAX (Mounting height) 81 (STAND OFF) 80 25.35 (.998) REF 41 "A" 40 0.30±0.10 0.15±0.05 0.13(.005) M (.012±.004) (.006± ...
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... Tel: (65) 281-0770 Fax: (65) 281-0220 F9707 FUJITSU LIMITED Printed in Japan To Top / Lineup / Index MB91103 Series All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...