r5f71374an80fpv Renesas Electronics Corporation., r5f71374an80fpv Datasheet - Page 11

• Manufacturer Part Number: r5f71374an80fpv
• Description: 32-bit Risc Microcomputer Superh?? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

5.6
5.7
5.8
Section 6 Interrupt Controller (INTC) .................................................................93
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5.5.2
5.5.3
5.5.4
Cases when Exceptions are Accepted .................................................................................. 87
Stack States after Exception Handling Ends ........................................................................ 88
Usage Notes ......................................................................................................................... 90
5.8.1
5.8.2
5.8.3
5.8.4
Features................................................................................................................................ 93
Input/Output Pins ................................................................................................................. 95
Register Descriptions ........................................................................................................... 96
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources................................................................................................................ 106
6.4.1
6.4.2
6.4.3
Interrupt Exception Handling Vector Table....................................................................... 108
Interrupt Operation............................................................................................................. 112
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 115
Data Transfer with Interrupt Request Signals .................................................................... 117
6.8.1
6.8.2
6.8.3
Usage Note......................................................................................................................... 119
Trap Instructions ..................................................................................................... 85
Illegal Slot Instructions ........................................................................................... 86
General Illegal Instructions..................................................................................... 86
Value of Stack Pointer (SP) .................................................................................... 90
Value of Vector Base Register (VBR) .................................................................... 90
Address Errors Caused by Stacking for Address Error Exception Handling .......... 90
Notes on Slot Illegal Instruction Exception Handling ............................................ 91
Interrupt Control Register 0 (ICR0)........................................................................ 97
IRQ Control Register (IRQCR) .............................................................................. 98
IRQ Status register (IRQSR) ................................................................................ 100
Interrupt Priority Registers A, D to F, and H to M (IPRA, IPRD to IPRF, and
IPRH to IPRM) ..................................................................................................... 103
External Interrupts ................................................................................................ 106
On-Chip Peripheral Module Interrupts ................................................................. 107
User Break Interrupt ............................................................................................. 107
Interrupt Sequence ................................................................................................ 112
Stack after Interrupt Exception Handling ............................................................. 115
Handling Interrupt Request Signals as Sources for DTC Activation and CPU
Interrupts............................................................................................................... 118
Handling Interrupt Request Signals as Sources for DTC Activation, but Not
CPU Interrupts ...................................................................................................... 118
Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not
DTC Activation..................................................................................................... 119
Rev. 1.00 Sep. 21, 2007 Page xi of xxvi