ep7309 Cirrus Logic, Inc., ep7309 Datasheet - Page 17

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ep7309

Manufacturer Part Number
ep7309
Description
Ep7309 Data Sheet
Manufacturer
Cirrus Logic, Inc.
Datasheet

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Static Memory Single Write Cycle
DS507F1
E X P R D Y
E X P C L K
W R IT E
W O R D
W O R D
n M W E
H A L F -
n M O E
n C S
A
D
Note:
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
valid timing under zero wait state conditions.
t
t
H W d
W D d
Figure 4. Static Memory Single Write Cycle Timing Measurement
t
t
t
EXs
C Sd
Ad
t
M W d
t
D v
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
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EXh
t
M W h
High-Performance, Low-Power System on Chip
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C Sh
EP7309
17

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