w78e516b Winbond Electronics Corp America, w78e516b Datasheet - Page 6

• Manufacturer Part Number: w78e516b
• Description: 8-bit Microcontroller
• Manufacturer: Winbond Electronics Corp America

5. FUNCTIONAL DESCRIPTION
The W78E516B architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be switched to
port2. The processor supports 111 different opcodes and references both a 64K program address
space and a 64K data storage space.
5.1 RAM
The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
• RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
• RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
• AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory with
Example,
CHPENR
CHPCON
MOV
MOV
ORL
MOV
MOV
MOV
MOVX
5.2 Timers 0, 1 and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
are R0 and R1 of the selected register bank.
R1 of the selected registers bank.
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting
the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the
instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD .
REG
REG
CHPENR, #87H
CHPENR, #59H
CHPCON, #00010000B
CHPENR, #00H
R0, #12H
A, #34H
@R0, A
F6H
BFH
; enable AUX-RAM
; Write 34h data to 12h address.
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Publication Release Date: April 22, 2008
W78E516B
Revision A12