w925e625 ETC-unknow, w925e625 Datasheet - Page 26
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w925e625
Manufacturer Part Number
w925e625
Description
8-bit Cid Microcontroller
Manufacturer
ETC-unknow
Datasheet
1.W925E625.pdf
(75 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
w925e625FG
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
CAS TONE PRESENT TIME REGISTER
The clock period of guard-time timer is 0.8582Ms. The default alert tone present time is 12.87Ms.
CASPT7-0: The pre-set data register for counting CAS tone present time. When CAS tone is detected
CAS TONE ABSENT TIME REGISTER
The clock period of guard-time timer is 0.8582Ms. The default alert tone absent time is 12.87Ms.
CASAT7-0: The pre-set data register for counting CAS tone absent time. When CAS tone is absent
SERIAL PORT CONTROL
SF1: Serial port interrupt flag. When 8-bits data transited completely, SF1 is set by hardware. SF1 is
LCDON: LCD waveform enable control. 0 to Disable LCD display, 1 to Enable LCD display.
REGON: Regulator on/off control. 0 to disable regulator, 1 to regulator.
REN1: Set REN1 from 0 to 1 to start the serial port1 to receive 8-bit serial data.
SFQ: SFQ=0 Serial clock output frequency is equal to f
SEDG: SEDG=0 Serial data latched at falling edge of clock, SCLK=Low initially.
CLKIO: CLKIO=0 P4.0(SCLK) work as output mode
SIO:
cleared when serial interrupt routine is executed or cleared by software.
SFQ=1 Serial clock output frequency is equal to f
SIO=0 P4.0 & P4.1 work as normal I/O pin
SIO=1 P4.0 & P4.1 work as Serial port1 function
Bit:
SEDG=1 Serial data latched at rising edge of clock, SCLK=High initially.
CLKIO=1 P4.0(SCLK) work as input mode
(ALGR low to high), the guard timer starts to up-count from 00H. As the guard timer is
equal to the value of CASPT, the exist of the CAS tone is accepted. ALGR changes to
low state to stop and reset the counter.
(ALGR high to low), the guard timer starts to up-count from 00H. As the guard timer is
equal to the value of CASAT, the finish of CAS tone is recognized. ALGR changes to high
state to stop and reset the counter.
Mnemonic: CASAT
Mnemonic: SCON1
Mnemonic: CASPT
SF1
7
Bit:
Bit:
LCDON
CASPT7 CASPT6 CASPT5 CASPT4 CASPT3 CASPT2 CASPT1 CASPT0
CASAT7 CASAT6 CASAT5 CASAT4 CASAT3 CASAT2 CASAT1 CASAT0
6
7
7
REGON
6
6
5
- 26 -
5
5
REN1
4
OSC
OSC
4
4
/2
/256
SFQ
3
(initial=0FH)
3
3
SEDG
Address: Beh
Address: BFh
Address: C0h
(initial=0FH)
(initial=00H)
2
2
2
W925E/C625
CLKIO
1
1
1
SIO
0
0
0