m40z300 STMicroelectronics, m40z300 Datasheet - Page 11

• Manufacturer Part Number: m40z300
• Description: Nvram Controller For Up To Eight Lpsram
• Manufacturer: STMicroelectronics

Caution:
2.3
2.4
2.5
battery capacity for the SNAPHAT
determine the amount of data retention available (see
Take care to avoid inadvertent discharge through V
been attached.
For a further more detailed review of lifetime calculations, please see Application Note
AN1012.
Power-on reset output
All microprocessors have a reset input which forces them to a known state when starting.
The M40Z300/W has a reset output (RST) pin which is guaranteed to be low within t
V
resistor should be chosen to control the rise time. This signal will be valid for all voltage
conditions, even when V
Once V
for t
Battery low pin
The M40Z300/W automatically performs battery voltage monitoring upon power-up, and at
factory-programmed time intervals of at least 24 hours. The Battery Low (BL) pin will be
asserted if the battery voltage is found to be less than approximately 2.5V. The BL pin will
remain asserted until completion of battery replacement and subsequent battery low
monitoring tests, either during the next power-up sequence or the next scheduled 24-hour
interval.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be
considered suspect, and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery back-up mode, the battery should be replaced. The SNAPHAT
replaced with valid V
The M40Z300/W only monitors the battery when a nominal V
Thus appli-cations which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique. The BL pin is an open drain output and an
appropriate pull-up resistor to V
V
I
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
CC
PFD
CC
REC
transients, including those produced by output switching, can produce voltage
(see
noise and negative going transients
CC
to allow the power supply to stabilize.
CC
Table
exceeds the power failure detect voltage V
is supplied. In order to insure data integrity during subsequent periods of
7). This signal is an open drain configuration. An appropriate pull-up
CC
applied to the device.
CC
equals V
CC
®
should be chosen to control the rise time.
of your choice can then be divided by this current to
SS
.
CC
bus. These transients can be reduced if
OUT
PFD
Table 13 on page
and E1
, an internal timer keeps RST low
CC
CC
bus. The energy stored in the
CON
is applied to the device.
- E4
®
CON
top should be
23).
after battery has
WPT
11/25
of