m40z300av STMicroelectronics, m40z300av Datasheet - Page 6

• Manufacturer Part Number: m40z300av
• Description: 3v Nvram Supervisor For Up To 8 Lpsrams
• Manufacturer: STMicroelectronics

M40Z300AV
OPERATION
The M40Z300AV, as shown in
can control up to four (eight, if placed in parallel)
standard low-power SRAMs. These SRAMs must
be configured to have the chip enable input dis-
able all other input signals. Most slow, low-power
SRAMs are configured like this, however many
fast SRAMs are not. During normal operating con-
ditions, the conditioned chip enable (E1
E4
pin with timing shown in
ble 7., page
to V
than 0.3V (I
When V
E1
of E. In this situation, the SRAM is unconditionally
write protected as V
ance threshold (V
THS pin must be tied to ground (as shown in
6., page
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time t
E1
write protecting the SRAM. A power failure during
Table 2. Truth Table
Figure 7. Address-Decode Time
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1
6/20
CON
CON
CON
OUT
E4
) output pins follow the chip enable (E) input
E
H
L
L
L
L
CON
to E4
to E4
. This switch has a voltage drop of less
11).
CC
.
OUT1
13. An internal switch connects V
A, B
E
E1 CON - E4 CON
CON
CON
degrades during a power failure,
).
are forced inactive independent
are unconditionally driven high,
PFD
Inputs
CC
B
X
H
H
L
L
). For the M40Z300AV, the
falls below an out-of-toler-
Figure 7., page 6
Figure 6., page
A
X
H
H
L
L
and
tAS
CON
Table
WPT
Ta-
CC
5,
to
,
E1
H
H
H
H
CON
L
tEDL
a WRITE cycle may corrupt data at the currently
addressed location, but does not jeopardize the
rest of the SRAM's contents. At voltages below
V
will be write protected within the Write Protect
Time (t
(see
As V
disconnects V
to V
(V
age V
I
When V
back to the supply voltage. Outputs E1
E4
mum) after the power supply has reached V
independent of the E input, to allow for processor
stabilization (see
Two to Four Decode
The M40Z300AV includes a 2 input (A, B) decoder
which allows the control of up to 4 independent
SRAMs. The Truth Table for these inputs is shown
in Table 2.
OUT2
PFD
SO
CON
OUT
). Below the V
Figure 7., page
CC
(min), the user can be assured the memory
(see
OHB
WPT
are held inactive for t
continues to degrade, the internal switch
. This occurs at the switchover voltage
CC
E2
) provided the V
Table 6., page
to the SRAM and can supply current
H
H
H
H
CON
L
rises above V
CC
Outputs
tEDH
and connects the internal battery
Figure 11., page
SO
6).
, the battery provides a volt-
E3
11).
AI02551
H
H
H
H
CON
L
CC
SO
, V
fall time exceeds t
CER
OUT
12).
(120ms maxi-
is switched
E4
H
H
H
H
CON
L
CON
PFD
CON
to
F
,
-