m40sz100y STMicroelectronics, m40sz100y Datasheet - Page 13

• Manufacturer Part Number: m40sz100y
• Description: 5v Or 3v Nvram Supervisor For Lpsram
• Manufacturer: STMicroelectronics

2.5
2.6
If a battery low is generated during a power-up sequence, this indicates that the battery is
below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be
considered suspect, and verified as correct. A fresh battery should be installed.
If a battery low indication is generated during the 24-hour interval check, this indicates that
the battery is near end of life. However, data is not compromised due to the fact that a
nominal V
battery back-up mode, the battery should be replaced.
The M40SZ100Y/W only monitors the battery when a nominal V
Thus applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique. The BL pin is an open drain output and an
appropriate pull-up resistor to V
Power-fail input/output
The Power-Fail Input (PFI) is compared to an internal reference voltage (independent from
the V
Output (PFO) will go low. This function is intended for use as an under-voltage detector to
signal a failing power supply. Typically PFI is connected through an external voltage divider
(see
regulated output of the V
voltage at PFI falls below V
M40SZ100Y/W or the microprocessor drops below the minimum operating voltage.
During battery back-up, the power-fail comparator turns off and PFO goes (or remains) low.
This occurs after V
irrespective of V
the inputs are recognized. At the end of this time, the power-fail comparator is enabled and
PFO follows PFI. If the comparator is unused, PFI should be connected to V
unconnected.
V
I
fluctuations, resulting in spikes on the V
capacitors are used to store energy which stabilizes the V
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in
Figure 9 on page
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, STMicroelectronics recommends
connecting a schottky diode from V
Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is
recommended for surface mount.
CC
CC
transients, including those produced by output switching, can produce voltage
Figure 5 on page
PFD
noise and negative going transients
comparator). If PFI is less than the power-fail threshold (V
CC
is supplied. In order to insure data integrity during subsequent periods of
PFI
14) is recommended in order to provide the needed filtering.
CC
for the write protect time (t
drops below V
8) to either the unregulated DC input (if it is available) or the
CC
PFI
regulator. The voltage divider can be set up such that the
several milliseconds before the regulated V
CC
should be chosen to control the rise time.
CC
PFD
CC
to V
CC
(min). When power returns, PFO is forced high,
that drive it to values below V
SS
bus. These transients can be reduced if
(cathode connected to V
REC
), which is the time from V
CC
bus. The energy stored in the
CC
is applied to the device.
PFI
), the Power-Fail
CC
SS
, anode to V
CC
by as much as
SS
PFD
input to the
and PFO left
(max) until
SS
13/25
).