ak4384 AKM Semiconductor, Inc., ak4384 Datasheet - Page 13

• Manufacturer Part Number: ak4384
• Description: 106db 192khz 24-bit 2ch ?? Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
The AK4384 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel immediately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channels go
to “H” only when the input data at both channels are continuously zeros for 8192 LRCK cycles. Zero detect function can
be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF
pin.
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
Notes:
MS0176-E-01
Zero Detection
Soft Mute Operation
(2) The analog output corresponding to the digital input has a group delay, GD.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
(1) ATT_DATA×ATT transition time (Table 10). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
(1020/fs) at ATT_DATA=255.
returned to ATT level by the same cycle.
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
SMUTE bit
Attenuation
AOUT
DZF pin
ATT Level
-∞
Figure 5. Soft Mute and Zero Detection
(1)
8192/fs
(4)
- 13 -
GD
(2)
(1)
GD
(3)
[AK4384]
2006/01