ak4352 AKM Semiconductor, Inc., ak4352 Datasheet

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ak4352

Manufacturer Part Number
ak4352
Description
2v & Low Power Multi-bit Dac
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
The AK4352 is an 18bit low voltage & power stereo DAC for digital audio system. The AK4352 uses the
new developed Multi-Bit
operation. The AK4352 includes post filter with single-ended output and does not need any external parts.
The AK4352 is suitable for the portable audio system like MD, etc as low power and small package.
M0040-E-02
SDATA
VDD
VSS
LRCK
BICK
PD
De-emphasis
Serial Input
DIF0
Multi-Bit
Sampling Rate Ranging: 8kHz 50kHz
On chip post filter
On chip Buffer with Single-ended Output
On chip Perfect filtering 8 times FIR interpolator
Digital Audio I/F format: 2’s compliment, MSB first
Digital de-emphasis for 44.1kHz sampling
Master clock: 256fs or 384fs
THD+N: -83dB@2V, -89dB@3V
D-Range: 94dB@2V, 96dB@3V
Output Voltage: 1.10Vpp@2V
Low Voltage Operation: 2V (1.8 3.6V)
Low power Dissipation: 6mW@2V
Very Small Package: 16pin TSSOP
Control
Interface
architecture, this new architecture achieves DR=94dB at low voltage
DEM
Passband: 20kHz
Passband Ripple: 0.06dB
Stopband Attenuation: 43dB
18bit MSB justified, 16/18bit LSB justified, I
DIF1
DAC
GENERAL DESCRIPTION
8X
Interpolator
8X
Interpolator
Clock Divider
FEATURES
MCLK
- 1 -
2V & Low Power Multi-Bit
CKS
Modulator
Modulator
LPF
2
LPF
VREF
S
AK4352
VCML
AOUTL
AOUTR
VCMR
DAC
[AK4352]
2000/11

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ak4352 Summary of contents

Page 1

... ASAHI KASEI The AK4352 is an 18bit low voltage & power stereo DAC for digital audio system. The AK4352 uses the new developed Multi-Bit architecture, this new architecture achieves DR=94dB at low voltage operation. The AK4352 includes post filter with single-ended output and does not need any external parts. ...

Page 2

... View PIN/FUNCTION Function Master Clock Pin Power-Down Pin When at “L”, the AK4352 is in power-down mode and is held in reset. The AK4352 should always be reset upon power-up. Serial Bit Input Clock Pin This clock is used to latch audio data. Audio Data Input Pin ...

Page 3

... AOUT (typ.@0dB)=1.10Vpp*VREF/2. *AKM assumes no responsibility for the usage beyond the conditions in this data sheet. M0040-E-02 ABSOLUTE MAXIMUM RATINGS Symbol min VDD -0.3 IIN - VIND -0.3 Ta -40 Tstg -65 Symbol min typ VDD 1.8 2.0 VREF - - 3 - [AK4352] max Units 4 VDD+0 150 C max Units 3.6 V VDD V 2000/11 ...

Page 4

... Note 5. In case of power-down mode, all digital input pins including clock pins (MCLK,BICK and LRCK) are held VDD or VSS. M0040-E-02 ANALOG CHARACTERISTICS 10k ; unless otherwise specified) L min (Note (Note 4) 1.02 10 (Note 5) (Note [AK4352] typ max Units -83 - 100 dB 0.1 0 ppm ...

Page 5

... Parameter High-Level Input Voltage Low-Level Input Voltage Input Leakage Current M0040-E-02 FILTER CHARACTERISTICS Symbol min typ 22. 14.7 - DIGITAL CHARACTERISTICS Symbol min VIH 75 VDD VIL - Iin - - 5 - [AK4352] max Units 20.0 kHz - kHz kHz dB 0. 1/fs 0 typ max Units - - VDD - 10 A 2000/11 ...

Page 6

... PD Pulse Width Note 8. Refer to the operating overview section “Audio Data Interface”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4352 can be reset by bringing PD = “L” to “H” only upon power up. n Timing Diagram LRCK ...

Page 7

... All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4352 is in normal operation mode ( PD = “H”). If these clocks are not provided, the AK4352 may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4352 should be in the power-down mode “ ...

Page 8

... ASAHI KASEI n Audio Serial Interface Format The AK4352 interfaces with external system by using SDATA, BICK and LRCK pins. Four types of data format are available and one of them is selected by setting DIF0 and DIF1. Format 0 is compatible with existing 16bit DACs and digital filters. Format 18bit version of format 0. Format 2 is similar to AKM ADCs and many DSP serial ports. ...

Page 9

... The AK4352 includes the digital de-emphasis filter (tc=50/ IIR filter. This filter corresponds to 44.1kHz sampling. The de-emphasis is enabled by setting DEM pin “H”. n Power-down The AK4352 is placed in the power-down mode by bringing PD pin “L” and the anlog outputs are floating(Hi-Z). Figure 5 shows an example of the system timing at the power-down and power-up. PD ...

Page 10

... ASAHI KASEI n System Reset The AK4352 should be reset once by bringing PD = “L” upon power-up. The internal timing starts clocking by LRCK “ ” upon exiting reset. Figure 6 shows the system connection diagram. An evaluation board [AKD4352] is available in order to allow an easy study on the layout of a surrounding circuit. ...

Page 11

... Grounding and Power Supply Decoupling Figure 6 shows the power supply connection example. VDD is supplied from analog supply in system. Decoupling capacitors for high frequency should be as near to the AK4352 device as possible, with the low value ceramic capacitor between VREF and VSS being the nearest. ...

Page 12

... ASAHI KASEI 16pin TSSOP (Unit: mm) *5 0.22 0.1 Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: M0040-E-02 PACKAGE 0.65 0.17 0.05 Detail A | 0.10 Epoxy Cu Solder plate - 12 - [AK4352] 1.10max 0.1 0.1 0-10 2000/11 ...

Page 13

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0040-E-02 MARKING AKM 4352VT XXYYY Contents of XXYYY XX: Lot# YYY: Date Code IMPORTANT NOTICE - 13 - [AK4352] 2000/11 ...

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