ak4396 AKM Semiconductor, Inc., ak4396 Datasheet - Page 18

• Manufacturer Part Number: ak4396
• Description: Advanced Multi-bit 192khz 24-bit ?? Dac
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
In serial mode, the AK4396 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4396
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4396 performs for
only PCM data.
[1] PCM Mode
The external clocks, which are required to operate the AK4396, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. When external clocks are changed, the AK4396 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4396 is in normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4396 should be in the power-down mode
(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L” → “H”) at power-up etc., the
AK4396 is in power-down mode until MCLK is supplied.
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency
corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,
the AK4396 should be reset by PDN pin. Quad speed mode is not supported in this mode.
MS0336-E-00
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
LRCK
D/A Conversion Mode
System Clock
fs
11.2896
12.2880
128fs
N/A
N/A
N/A
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)
Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)
16.9344
18.4320
192fs
N/A
N/A
N/A
DFS0 pin
H
L
11.2896
12.2880
22.5792
24.5760
8.1920
Table 1. PCM/DSD Mode Control
256fs
OPERATION OVERVIEW
Normal Speed Mode
Double Speed Mode
D/P bit
0
1
MCLK (MHz)
12.2880
16.9344
18.4320
33.8688
36.8640
384fs
- 18 -
Sampling Rate (fs)
Interface
PCM
DSD
16.3840
22.5792
24.5760
512fs
N/A
N/A
54kHz ∼ 108kHz
30kHz ∼ 54kHz
24.5760
33.8688
36.8640
768fs
N/A
N/A
36.8640
1152fs
N/A
N/A
N/A
N/A
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
[AK4396]
BICK
64fs
2004/08