71m6541g-igtr/f Maxim Integrated Products, Inc., 71m6541g-igtr/f Datasheet - Page 115

• Manufacturer Part Number: 71m6541g-igtr/f
• Description: 71m6541d/71m6541f/71m6542f Energy Meter Ics
• Manufacturer: Maxim Integrated Products, Inc.

v1.1
Name
FLSH_ERASE[7:0]
FLSH_MEEN
FLSH_PEND
FLSH_PGADR[5:0]
FLSH_PSTWR
FLSH_PWE
FLSH_RDE
FLSH_UNLOCK[3:0]
FLSH_WRE
SFR 94[7:0]
SFR B7[7:2]
SFR B2[1]
SFR B2[3]
SFR B2[2]
SFR B2[0]
Location
2702[7:4]
2702[2]
2702[1]
© 2008–2011 Teridian Semiconductor Corporation
Rst Wk Dir
0
0
0
0
0
0
–
0
–
0
0
0
0
0
0
–
0
–
R/W
R/W
R/W
W
W
W
R
R
R
This bit is automatically reset after each byte written to flash. Writes to this bit
are inhibited when interrupts are enabled.
Description
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash
Page Erase cycle. Specific patterns are expected for FLSH_ERASE in order
to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to
0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to
Any other pattern written to FLSH_ERASE has no effect.
Mass Erase Enable
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Indicates that a timed flash write is pending. If another flash write is attempted,
it is ignored.
Flash Page Erase Address
FLSH_PGADR[5:0] – Flash Page Address (page 0 thru 63) that is erased during
the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables timed flash writes. When 1, and if CE_E = 1, flash write requests are
stored in a one-element deep FIFO and are executed when CE_BUSY falls.
FLSH_PEND can be read to determine the status of the FIFO. If
FLSH_PSTWR = 0 or if CE_E = 0, flash writes are immediate.
Program Write Enable
0 = MOVX commands refer to External RAM Space, normal operation (default).
1 = MOVX @DPTR,A moves A to External Program Space (Flash) @ DPTR.
Indicates that the flash may be read by ICE or SPI slave. FLSH_RDE =
(!SECURE)
Must be a ‘2’ to enable any flash modification. See the description of Flash
security for more details.
Indicates that the flash may be written through ICE or SPI slave ports.
FLSH_PGADR[5:0] (SFR 0xB7[7:2]).
FLSH_MEEN and the ICE port must be enabled.
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