71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet - Page 7

• Manufacturer Part Number: 71m6543h-igtr/f
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

71M6543F/H Data Sheet
Table 49: Data/Direction Registers for SEGDIO16 to SEGDIO31 ........................................................... 60
Table 50: Data/Direction Registers for SEGDIO32 to SEGDIO45 ........................................................... 61
Table 51: Data/Direction Registers for SEGDIO51 to SEGDIO55 ........................................................... 61
Table 52: LCD_VMODE Configurations .................................................................................................. 62
Table 53: LCD Configurations ................................................................................................................ 63
Table 54: LCD Data Registers for SEGDIO46 to SEGDIO55 .................................................................. 64
Table 55: EECTRL Bits for 2-pin Interface ............................................................................................... 65
Table 56: EECTRL Bits for the 3-wire Interface ....................................................................................... 66
Table 57: SPI Transaction Fields ........................................................................................................... 68
Table 58: SPI Command Sequences ..................................................................................................... 69
Table 59: SPI Registers ......................................................................................................................... 69
Table 60: TMUX[4:0] Selections ............................................................................................................ 72
Table 61: TMUX2[4:0] Selections ........................................................................................................... 73
Table 62: Available Circuit Functions ..................................................................................................... 76
Table 63: VSTAT[2:0] (SFR 0xF9[2:0]) ................................................................................................... 79
Table 64: Wake Enable and Flag Bits .................................................................................................... 81
Table 65: Wake Bits .............................................................................................................................. 82
Table 66: Clear Events for WAKE flags .................................................................................................. 83
Table 67: GAIN_ADJn Compensation Channels (Figure 2, Figure 30, Table 1) ...................................... 90
Table 68: GAIN_ADJx Compensation Channels (Figure 3, Figure 31, Table 2) ...................................... 92
Table 69: I/O RAM Map – Functional Order, Basic Configuration ........................................................... 97
Table 70: I/O RAM Map – Functional Order ........................................................................................... 99
Table 71: I/O RAM Map – Alphabetical Order ...................................................................................... 103
Table 72. Info Page Trim Fuses ........................................................................................................... 117
Table 73: CE EQU[2:0] Equations and Element Input Mapping ............................................................ 120
Table 74: CE Raw Data Access Locations ........................................................................................... 121
Table 75: CESTATUS Register .............................................................................................................. 122
Table 76: CESTATUS Bit Definitions...................................................................................................... 122
Table 77: CECONFIG Register ............................................................................................................. 122
Table 78: CECONFIG Bit Definitions (CE RAM 0x20) ........................................................................... 123
Table 79: Sag Threshold, Phase Measurement, and Gain Adjust Control ............................................. 124
Table 80: CE Transfer Variables (with Shunts) ..................................................................................... 124
Table 81: CE Transfer Variables (with CTs) ......................................................................................... 125
Table 82: CE Energy Measurement Variables (with Shunts)................................................................. 125
Table 83: CE Energy Measurement Variables (with CTs) ..................................................................... 125
Table 84: Other Transfer Variables ...................................................................................................... 126
Table 85: CE Pulse Generation Parameters......................................................................................... 127
Table 86: CE Parameters for Noise Suppression and Code Version..................................................... 128
Table 87: CE Calibration Parameters ................................................................................................... 129
Table 88: Absolute Maximum Ratings .................................................................................................. 132
Table 89: Recommended External Components .................................................................................. 133
Table 90: Recommended Operating Conditions ................................................................................... 133
Table 91: Input Logic Levels ................................................................................................................ 134
Table 92: Output Logic Levels ............................................................................................................. 134
Table 93: Battery Monitor Performance Specifications (TEMP_BAT = 1) ............................................... 135
Table 94. Temperature Monitor ............................................................................................................ 135
Table 95: Supply Current Performance Specifications .......................................................................... 136
Table 96: V3P3D Switch Performance Specifications ........................................................................... 137
Table 97: 2.5 V Voltage Regulator Performance Specifications ............................................................ 137
Table 98: Low-Power Voltage Regulator Performance Specifications ................................................... 138
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