71m6521be Maxim Integrated Products, Inc., 71m6521be Datasheet - Page 33

• Manufacturer Part Number: 71m6521be
• Description: Energy Meter Ic
• Manufacturer: Maxim Integrated Products, Inc.

External Interrupts
The 71M6521BE MPU allows seven external interrupts. These are connected as shown in Table 45. The direction of interrupts
2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU
literature states that interrupt 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 45.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description for more detail.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that XFER_BUSY,
FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition to the interrupt 6, 4, and 2 enable and
flag bits.
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER
through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte, common practice
would be to clear them with a bit operation. This is to be avoided. The hardware implements bit operations as a byte wide read-
modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to
be cleared. The flag bits are configured in hardware to ignore ones written to them.
V1.0
EX_FWCOL
EX_XFER
EX_PLL
Name
EX0
EX1
EX2
EX3
EX4
EX5
EX6
Interrupt Enable
Interrupt
External
0
1
2
3
4
5
6
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
Location
2002[0]
2007[4]
2007[5]
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY
© 2005-2008 TERIDIAN Semiconductor Corporation
Table 46: Interrupt Enable and Flag Bits
Table 45: External MPU Interrupts
IE_PLLFALL
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
Connection
IE_WAKE
IE_XFER
Name
IE_PB
IEX2
IEX3
IEX4
IEX5
IEX6
IE0
IE1
Interrupt Flag
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[3]
SFR E8[2]
SFR 88[1]
SFR 88[3]
SFRE8[6]
SFRE8[7]
SFRE8[5]
SFRE8[4]
Location
see DIO_Rx
see DIO_Rx
Polarity
falling
falling
falling
falling
rising
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
FWCOL0 interrupt (int 2)
FWCOL1 interrupt (int 2)
PLL_OK rise interrupt (int 4)
PLL_OK fall interrupt (int 4)
AUTOWAKE flag
PB flag
Energy Meter IC
Interrupt Description
Flag Reset
automatic
automatic
automatic
automatic
automatic
automatic
manual
71M6521BE
DATA SHEET
JANUARY 2008
Page: 33 of 97